JPS6334966A - Frame for resin-sealed semiconductor device - Google Patents
Frame for resin-sealed semiconductor deviceInfo
- Publication number
- JPS6334966A JPS6334966A JP17951286A JP17951286A JPS6334966A JP S6334966 A JPS6334966 A JP S6334966A JP 17951286 A JP17951286 A JP 17951286A JP 17951286 A JP17951286 A JP 17951286A JP S6334966 A JPS6334966 A JP S6334966A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- resin
- lead part
- semiconductor chip
- conductor plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000011347 resin Substances 0.000 abstract description 12
- 229920005989 resin Polymers 0.000 abstract description 12
- 238000007789 sealing Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract 6
- 238000000034 method Methods 0.000 abstract 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、樹脂封止形半導体装置用フレームに関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame for a resin-sealed semiconductor device.
従来の樹脂封止形半導体装置用フレーム(以下単にフレ
ームという)として、第3図に示すものがあった。第3
図において、1は半導体チップ(図示せず)を接着する
導電板、2は接続用ワイヤを介して前記半導体チップと
電気的に接続されるリードで、複数のリード2でリード
部20が形成される。3,4は前記導電板1とリード2
を固定するためのタイバーおよび外枠であり、樹脂封止
後除去される。As a conventional frame for a resin-sealed semiconductor device (hereinafter simply referred to as frame), there is one shown in FIG. Third
In the figure, 1 is a conductive plate to which a semiconductor chip (not shown) is bonded, 2 is a lead electrically connected to the semiconductor chip via a connecting wire, and a lead portion 20 is formed by a plurality of leads 2. Ru. 3 and 4 are the conductive plate 1 and the lead 2
These are the tie bars and outer frame for fixing, and are removed after resin sealing.
これら導電板1.リード部20.タイバー3゜外枠4を
まとめてフレームと称している。These conductive plates 1. Lead part 20. The tie bar 3° and the outer frame 4 are collectively referred to as a frame.
第4図は樹脂封止後のフレームを示す図であり、5は樹
脂を示している。FIG. 4 is a diagram showing the frame after being sealed with resin, and 5 indicates the resin.
第3図に示す従来のフレームは平板材料をパンチングま
たはエツチングすることにより成形される。The conventional frame shown in FIG. 3 is formed by punching or etching a flat sheet of material.
したがって、従来のフレーム−では一定の外形寸法を有
する樹脂封止形半導体装置を製造する場合、導電板1と
リード2が樹脂5内に納まるようにフレーム寸法を設計
しなければならず、半導体チップの寸法が規定より大き
いときには、チップ寸法が小さくなるように再設計した
り、樹脂封止形半導体装置全体の外形寸法を犬きくする
ことを許容することが必要であり、また、設計上余裕の
ない場合には、接続用ワイヤの形状を悪くしたり、リー
ド部20の樹脂埋没面積の不足による信頼性の低下等の
問題点があった。Therefore, when manufacturing a resin-sealed semiconductor device with a fixed external dimension using a conventional frame, the frame dimensions must be designed so that the conductive plate 1 and the leads 2 are accommodated within the resin 5, and the semiconductor chip If the dimensions of the resin molded semiconductor device are larger than the specified specifications, it is necessary to redesign the chip so that it is smaller, or to allow the external dimensions of the entire resin-sealed semiconductor device to be increased. If not, there are problems such as the shape of the connecting wire becomes poor and the reliability decreases due to insufficient resin-embedded area of the lead portion 20.
この発明は、上記のような問題点を解消するためになさ
れたもので、導電板とリード部を大きくできるとともに
、独立して寸法設計ができるフレームを得ることを目的
とする。This invention was made to solve the above-mentioned problems, and aims to provide a frame in which the conductive plate and the lead portion can be made larger and whose dimensions can be designed independently.
この発明に係るフレームは、導電板と、リード部とを隔
てて同一フレームに一体に形成しておき、フレームを半
導体チップ上に折り重ねることにより、リード部が導電
板上の所要位置にくる構成としたものである。The frame according to the present invention has a structure in which a conductive plate and a lead part are separated and integrally formed in the same frame, and by folding the frame over a semiconductor chip, the lead part is placed at a desired position on the conductive plate. That is.
この発明のフレームにおいては、導電板とリード部の寸
法が独立に設計できることから、それぞれ樹脂封止可能
な最大限まで大きく設計できる。In the frame of the present invention, since the dimensions of the conductive plate and the lead portion can be designed independently, each can be designed to be as large as possible for resin sealing.
以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図、第2図はこの発明の一実施例を示すフレームの
平面図および折り重ねた状態の斜視図である。第1図、
第2図において、第3図、第4図と同一符号は同じもの
を示し、6は前記導電板1上にダイポンドされた半導体
チップである。また、リード部2oは、導電板1を隔て
て同一フレームに一体に配置される。FIGS. 1 and 2 are a plan view and a perspective view of a folded frame showing an embodiment of the present invention. Figure 1,
In FIG. 2, the same reference numerals as in FIGS. 3 and 4 indicate the same parts, and 6 is a semiconductor chip die-bonded on the conductive plate 1. In FIG. Further, the lead portion 2o is arranged integrally on the same frame with the conductive plate 1 in between.
上記第1図のように構成されたフレームをタイバー3の
所要箇所から半導体チップS上に折り重ねることにより
、リード部20が導電板1の上にせり出し、第2図に示
すように、リード部20は導電板1上の所要位置に配置
されることになる。By folding the frame configured as shown in FIG. 1 above onto the semiconductor chip S from the required locations of the tie bars 3, the lead portions 20 protrude above the conductive plate 1, and as shown in FIG. 20 will be placed at a predetermined position on the conductive plate 1.
その後、半導体チップ6とリード部2oの所定のり一ド
2とを接続用ワイヤ7で接続し、図示はしないが樹脂5
により封止される。After that, the semiconductor chip 6 and the predetermined glue 2 of the lead part 2o are connected with the connecting wire 7, and the resin 5
sealed by.
なお、上記実施例では、デュアルインライン形半導体装
置を例にとって説明したが、シングルインライン等、類
似構造のフレームにも適用できる。In the above embodiments, a dual in-line type semiconductor device has been described as an example, but the present invention can also be applied to a frame with a similar structure such as a single in-line type.
以上説明したようにこの発明は、半導体チップがグイポ
ンドされる導電板と、半導体チップと接続用ワイヤで接
続されるリード部とを隔てて同一フレームに一体に形成
してなり、このフレームを半導体チップ上に折り重ねる
ことによってリード部を導電板上の所要位置に配置せし
めるようにしたので、導電板やリード部の寸法がそれぞ
れ独立に、かつ樹脂封止可能な最大限まで拡大でき、大
きなチップを小さなパッケージに納めることができる効
果がある。As explained above, in the present invention, a conductive plate on which a semiconductor chip is grounded and a lead part connected to the semiconductor chip with a connecting wire are separated and integrally formed in the same frame. By folding the leads upward, the lead parts can be placed at the desired positions on the conductive plate, allowing the dimensions of the conductive plate and lead parts to be expanded independently and to the maximum extent that can be sealed with resin, making it possible to accommodate large chips. It has the advantage of being able to fit into a small package.
第1図はこの発明の一実施例を示す樹脂封止形半導体装
置用フレームの平面図、第2図は折り重ねた状態を示す
斜視図、第3図は従来の樹脂封止形半導体装置用フレー
ムの平面図、第4図は樹脂封止後の樹脂封止形半導体装
置用フレームの状態を示す平面図である。
図において、1は導電板、2はリード、3はタイバー、
4は外枠、5は樹脂、6は半導体チ、ツブ、7は接続用
ワイヤ、2oはリード部である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 (外2名)第1図
第2図
7糧層し弔71ゴ
第3図
手続補正書く自発)
特許庁長官殿 謁1、堪性
の表示 特願昭61−179512号2、発明の名
称 ’34 RN封止形半導体装置用フレーム3、補
正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目2番3号。
名 称 (601)三菱電機株式会社代表者志岐守哉
4、代理人
住 所 東京都千代田区丸の内二丁目2番3号5
、補正の対象
明細書の特許請求の範囲のl111.発明の詳細な脱力
の欄および図面
6、補正の内容
(1) 明細書の特許請求の範囲を別紙のように補正
する。
(2)明細書第4頁8行、第5頁5行の「グイポンド」
を、それぞれ「グイボンド」と補正する。
(3) 第1図、第4図を別紙のように補正する。
以 上
2、特許請求の範囲
半導体チップがグイエンドされろ導電板と、前記半導体
チップに接続用ワイヤで接続されるリード部とを備又た
樹脂封止形半導体装置用フレームにおいて、前記導電板
と、リード部とを隔てて同一フレームに一体に形成して
なり、前記フレームを前記半導体チップ上に折り重ねる
ことにより、前記リード部が前記導電板上の所要位置に
くる構成としたことを特徴とする樹脂封止形半導体装置
用7レーム。
第1図
20=ソー ト地Fig. 1 is a plan view of a frame for a resin-sealed semiconductor device showing an embodiment of the present invention, Fig. 2 is a perspective view showing a folded state, and Fig. 3 is a frame for a conventional resin-sealed semiconductor device. A plan view of the frame, FIG. 4 is a plan view showing the state of the resin-sealed semiconductor device frame after resin sealing. In the figure, 1 is a conductive plate, 2 is a lead, 3 is a tie bar,
4 is an outer frame, 5 is a resin, 6 is a semiconductor chip, a tab, 7 is a connecting wire, and 2o is a lead portion. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1, Figure 2, Figure 7, Condolences, 71 Figures, Figure 3, Procedural amendments on his own initiative) Audience to the Commissioner of the Japan Patent Office 1, Indication of Compliance Patent Application No. 179512/1983 2. Title of the invention '34 Frame for RN-sealed semiconductor device 3, Relationship to the case of the person making the amendment Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo. Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, l111. of the claims of the specification subject to amendment. Detailed description of the invention, drawing 6, contents of amendment (1) The claims of the specification are amended as shown in the attached sheet. (2) “Guypond” on page 4, line 8 and page 5, line 5 of the specification
are respectively corrected as "Guibond". (3) Correct figures 1 and 4 as shown in the attached sheet. 2. Claims A frame for a resin-sealed semiconductor device comprising a conductive plate on which a semiconductor chip is connected, and a lead portion connected to the semiconductor chip with a connecting wire, wherein the conductive plate and , formed integrally with the same frame separated from the lead portion, and by folding the frame over the semiconductor chip, the lead portion is placed at a desired position on the conductive plate. 7 rams for resin-sealed semiconductor devices. Figure 1 20 = Sort area
Claims (1)
チップに接続用ワイヤで接続されるリード部とを備えた
樹脂封止形半導体装置用フレームにおいて、前記導電板
と、リード部とを隔てて同一フレームに一体に形成して
なり、前記フレームを前記半導体チップ上に折り重ねる
ことにより、前記リード部が前記導電板上の所要位置に
くる構成としたことを特徴とする樹脂封止形半導体装置
用フレーム。In a resin-sealed semiconductor device frame comprising a conductive plate to which a semiconductor chip is die-bonded, and a lead part connected to the semiconductor chip with a connecting wire, the conductive plate and the lead part are separated from each other in the same frame. A frame for a resin-sealed semiconductor device, characterized in that the lead portion is placed at a desired position on the conductive plate by folding the frame over the semiconductor chip. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17951286A JPS6334966A (en) | 1986-07-29 | 1986-07-29 | Frame for resin-sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17951286A JPS6334966A (en) | 1986-07-29 | 1986-07-29 | Frame for resin-sealed semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6334966A true JPS6334966A (en) | 1988-02-15 |
Family
ID=16067089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17951286A Pending JPS6334966A (en) | 1986-07-29 | 1986-07-29 | Frame for resin-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6334966A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5724726A (en) * | 1992-06-05 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Method of making leadframe for lead-on-chip (LOC) semiconductor device |
DE4345303C2 (en) * | 1992-06-05 | 2003-12-04 | Mitsubishi Electric Corp | Lead wire frames for use in manufacturing a LOC structure semiconductor device and method for manufacturing a LOC structure semiconductor device |
-
1986
- 1986-07-29 JP JP17951286A patent/JPS6334966A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5724726A (en) * | 1992-06-05 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Method of making leadframe for lead-on-chip (LOC) semiconductor device |
US5763829A (en) * | 1992-06-05 | 1998-06-09 | Mitsubishi Denki Kabushiki Kaisha | Leadframe including frame-cutting slit for lead-on-chip (LOC) semiconductor device and semiconductor device incorporating the leadframe |
US5900582A (en) * | 1992-06-05 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Lead frame including frame-cutting slit for lead-on-chip (LOC) semiconductor device and semiconductor device incorporating the lead frame |
DE4345303C2 (en) * | 1992-06-05 | 2003-12-04 | Mitsubishi Electric Corp | Lead wire frames for use in manufacturing a LOC structure semiconductor device and method for manufacturing a LOC structure semiconductor device |
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