JP2918574B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2918574B2 JP2918574B2 JP1251949A JP25194989A JP2918574B2 JP 2918574 B2 JP2918574 B2 JP 2918574B2 JP 1251949 A JP1251949 A JP 1251949A JP 25194989 A JP25194989 A JP 25194989A JP 2918574 B2 JP2918574 B2 JP 2918574B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor chips
- bonding
- semiconductor device
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体チップの高集積化技術、特に、複数の
半導体チップを１つの封止部材内に実装して高集積化を
行うために用いて効果のある技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for a high integration technique of a semiconductor chip, particularly, for implementing a high integration by mounting a plurality of semiconductor chips in one sealing member. And effective technology.
従来より、ICなどの半導体装置は、１つのチップの各
ボンディングパッドにリードをボンディングし、この
後、樹脂モールドなどにより絶縁ならびに固化する工程
を経て作られる。2. Description of the Related Art Conventionally, a semiconductor device such as an IC is manufactured through a process in which leads are bonded to respective bonding pads of one chip, and thereafter, insulation and solidification are performed by a resin mold or the like.
ところで、本発明者は、半導体装置の高集積化につい
て検討した。By the way, the present inventor has studied high integration of a semiconductor device.
以下、本発明者によって検討された技術であり、その
概要は次の通りである。The following is a technique studied by the present inventors, and an outline thereof is as follows.
すなわち、半導体装置にあって、高集積化を図るに
は、チップ内の半導体チップ数を可能な限り増やすこと
であるが、これに伴ってパッド数が増える場合には、リ
ードピッチを確保しながらリード数を増やすことは難し
い。That is, in a semiconductor device, in order to achieve high integration, it is necessary to increase the number of semiconductor chips in a chip as much as possible. It is difficult to increase the number of leads.
そこで、「日経マイクロデバイス」1988年５月号、54
頁〜57頁に示すように、ダイ・パッドを無くし、チップ
の上または下にインナー・リードを引き回して接続を行
う方法が提案されている（この他、特開昭58−192354
号、特開昭61−50295号、特開昭60−167454号、特開昭6
1−500245号、特開昭61−218139号及び特開昭61−24195
9号などがある）。Therefore, "Nikkei Micro Devices", May 1988, 54
As shown on pp. 57-57, there has been proposed a method of eliminating the die pad and connecting the inner leads above or below the chip by connecting the inner leads (see also JP-A-58-192354).
No., JP-A-61-50295, JP-A-60-167454, JP-A-6
No. 1-500245, JP-A-61-218139 and JP-A-61-24195
No. 9).
しかし、このような半導体装置にあっては、１パッケ
ージ内に１チップの実装のみとしているため、リード接
続構造に工夫を凝らしても高集積化には限界がある。However, in such a semiconductor device, since only one chip is mounted in one package, high integration is limited even if the lead connection structure is devised.
そこで、複数の半導体チップを非導電性の接着剤など
で一体化し、この一面に設けたリードフレームによって
半導体チップのボンディングパッドの各々にボンディン
グワイヤを接続する構成とし、高集積化を図ることが提
案されている。メモリなどでは、アドレスバスやデータ
バスを並列接続することが可能であることから、積層化
によって高集積化を図ることができる。Therefore, it has been proposed to integrate a plurality of semiconductor chips with a non-conductive adhesive or the like, and connect a bonding wire to each of the bonding pads of the semiconductor chip by a lead frame provided on this one surface, thereby achieving high integration. Have been. In a memory or the like, since address buses and data buses can be connected in parallel, high integration can be achieved by stacking.
しかし、上記した従来の半導体装置にあっては、複数
個の半導体チップの各ボンディングパッドに対するワイ
ヤ接続は全てリードフレームを始点とし、各リードに複
数のワイヤを接続する構成がとられていた。このため、
ボンディングワイヤの引き回しが複雑化し、ワイヤが長
くなり、さらに各半導体チップに対するワイヤが平行配
設することによりワイヤ接触を生じ、あるいは高速動作
を損なうなどが本発明者によって見出された。However, in the above-described conventional semiconductor device, the wire connection to each bonding pad of a plurality of semiconductor chips is all started from a lead frame, and a plurality of wires are connected to each lead. For this reason,
The present inventor has found that the routing of the bonding wires becomes complicated, the wires become longer, and furthermore, the wires are arranged in parallel with each semiconductor chip, thereby causing wire contact or impairing the high-speed operation.
そこで、本発明の目的は、複数のチップを１つのパッ
ケージに最短のワイヤ接続で実装して高集積化を図るこ
とのできる技術を提供することにある。Therefore, an object of the present invention is to provide a technique capable of mounting a plurality of chips in one package with the shortest wire connection to achieve high integration.
本発明の前記目的と新規な特徴は、本明細書の記述及
び添付図面から明らかになるであろう。The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの
概要を説明すれば、以下の通りである。The outline of typical inventions among the inventions disclosed in the present application will be described as follows.
すなわち、一主面に複数個のボンディングパッドを有
する平面形状が大小異なる二つの半導体チップが、前記
各ボンディングパッド群が同一方向を向くとともに露出
し、かつ、両半導体チップ間に複数本のリードが介在さ
れた状態で重ね合わされており、前記各リードと前記各
ボンディングパッドとが各ワイヤによって電気的に接続
されていることを特徴とする。That is, two semiconductor chips having a plurality of bonding pads on one main surface and having different planar shapes are different in size while the bonding pad groups face in the same direction, and a plurality of leads are provided between the two semiconductor chips. The leads are overlapped with each other, and the leads and the bonding pads are electrically connected by wires.
両半導体チップのボンディングパッド群が同一方向を
向いているため、同一方向からワイヤボンディングする
ことができるとともに、最短距離でワイヤを接続するこ
とができる。最短距離でワイヤを接続させることより、
高速動作に対応することができる。両方の半導体チップ
の重合面と反対側の主面のそれぞれを放熱面に設定する
ことができるため、放熱性能を向上させることができ
る。Since the bonding pad groups of both semiconductor chips face in the same direction, wire bonding can be performed from the same direction, and wires can be connected at the shortest distance. By connecting wires at the shortest distance,
High-speed operation can be supported. Since each of the main surfaces opposite to the overlapping surface of both semiconductor chips can be set as the heat dissipation surface, the heat dissipation performance can be improved.
第１図は本発明による半導体装置の一実施例を示す平
面図、第２図は第１図の主要部を示す正面断面図であ
る。FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a front sectional view showing a main part of FIG.
本発明においては、4MビットDRAM（ダイナミック・ラ
ム）、16ビットDRAMなどのメモリモジュールを構成する
場合を例に説明する。また、ここでは、共に同一特性、
同一回路でサイズのみが異なる２つの半導体チップを用
いて高集積化を図るものとしている。In the present invention, a case where a memory module such as a 4-Mbit DRAM (dynamic RAM) or a 16-bit DRAM is configured will be described as an example. Here, both have the same characteristics,
It is intended to achieve high integration by using two semiconductor chips which differ only in size in the same circuit.
第１図及び第２図に示すように、サイズが大きく且つ
周辺部に所定数のボンディングパッド1aの設けられた半
導体チップ１の片面（表面）に絶縁性のフィルム２を接
着固定し、この表面に所定のパターン形状のリードフレ
ーム３をボンディングパッド1aに対向させて配設し、接
着固定する。さらにリードフレーム３の表面を覆うよう
に絶縁性のフィルム４を配設し、このフィルム４上に半
導体チップ１よりもサイズの小さい半導体チップ５を接
着固定する。半導体チップ５の周辺部には、リードフレ
ーム３及び半導体１のボンディングパッド1aに対向させ
てボンディングパッド5aが設けられている。As shown in FIGS. 1 and 2, an insulating film 2 is bonded and fixed to one surface (front surface) of a semiconductor chip 1 having a large size and a predetermined number of bonding pads 1a provided on the periphery. Then, a lead frame 3 having a predetermined pattern is arranged so as to face the bonding pad 1a, and is fixed by bonding. Further, an insulating film 4 is provided so as to cover the surface of the lead frame 3, and a semiconductor chip 5 smaller in size than the semiconductor chip 1 is bonded and fixed on the film 4. A bonding pad 5a is provided on the periphery of the semiconductor chip 5 so as to face the lead frame 3 and the bonding pad 1a of the semiconductor 1.
この場合、フィルム２はリードフレーム３の載置幅相
当、フィルム４は半導体チップ５のサイズ相当の大きさ
とし、その配置位置もリードフレーム３及び半導体チッ
プ５の各設置位置に合致させる。また、リードフレーム
３の端部は、半導体チップ１上に一部が露出するように
配設される。In this case, the film 2 has a size corresponding to the mounting width of the lead frame 3, and the film 4 has a size corresponding to the size of the semiconductor chip 5, and the arrangement position thereof is also matched with the installation position of the lead frame 3 and the semiconductor chip 5. The end of the lead frame 3 is disposed on the semiconductor chip 1 such that a part thereof is exposed.
ボンディングパッド1a及び5aの各々とリードフレーム
３とは、ボンディングワイヤ６によって接続される。Each of the bonding pads 1a and 5a and the lead frame 3 are connected by a bonding wire 6.
このような構成により、各半導体チップに対するボン
ディングワイヤ６の引き出し方向が互いに逆方向に展開
し、接触などの恐れがないと共に最短距離でワイヤ接続
を行うことができる。したがって、高速動作にも適して
いる。また、放熱面を表面に出すことができるので、法
熱処理にも有利な形状となる。With such a configuration, the pull-out directions of the bonding wires 6 with respect to the respective semiconductor chips are developed in directions opposite to each other, and there is no fear of contact or the like, and the wire connection can be performed in the shortest distance. Therefore, it is suitable for high-speed operation. Further, since the heat radiation surface can be exposed to the surface, the shape is advantageous for the method heat treatment.
以上のように本発明では、現在、半導体メモリの開発
過程で、最初に設計されたチップに対し、さらに縮小設
計されたシュリンクチップが開発されていることを利用
すると、上記実施例に示したような複数チップによる高
集積化（チップ数ｎのｎ倍に集積度を上げることが可）
を容易に達成することができる。As described above, the present invention takes advantage of the fact that, in the process of developing a semiconductor memory, a shrink chip that is further reduced in design is developed for a chip that was originally designed. High integration with multiple chips (integration can be increased to n times the number of chips n)
Can be easily achieved.
以上本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものでは無く、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. .
なお、前記各実施例においては、半導体チップ１と半
導体チップ５の各ボンディングパッドが同一方向にある
ものとしたが、一方の半導体チップのボンディングパッ
ドを90度ずらした方向へ設けるなども可能である。In the above embodiments, the bonding pads of the semiconductor chip 1 and the semiconductor chip 5 are in the same direction. However, the bonding pads of one semiconductor chip may be provided in a direction shifted by 90 degrees. .
本願において開示される発明のうち、代表的なものに
よって得られる効果を簡単に説明すれば、下記の通りで
ある。The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
各半導体チップのボンディングパッドが同一方向を向
いているため、ワイヤボンディングを同一方向から実施
することができるとともに、最短距離でワイヤを接続す
ることができる。最短距離でワイヤを接続させることに
より、高速動作に対応することができる。両方の半導体
チップの重合面と反対側の主面のそれぞれを放熱面に設
定することができるため、放熱性能を向上させることが
できる。Since the bonding pads of each semiconductor chip face in the same direction, wire bonding can be performed from the same direction, and wires can be connected at the shortest distance. By connecting the wires at the shortest distance, high-speed operation can be supported. Since each of the main surfaces opposite to the overlapping surface of both semiconductor chips can be set as the heat dissipation surface, the heat dissipation performance can be improved.
第１図は本発明による半導体装置の一実施例を示す平面
図である。 第２図は第１図の主要部を示す正面断面図である。 1,5…半導体チップ、1a,5a…ボンディングパッド、2,4
…絶縁性のフィルム、３…リードフレーム、6…ボンデ
ィングワイヤ。FIG. 1 is a plan view showing one embodiment of a semiconductor device according to the present invention. FIG. 2 is a front sectional view showing a main part of FIG. 1,5… semiconductor chip, 1a, 5a … bonding pad, 2, 4
... insulating film, 3 ... lead frame, 6 ... bonding wire.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭58−130553（ＪＰ，Ａ) 特開 昭60−94756（ＪＰ，Ａ) 実開 昭63−87847（ＪＰ，Ｕ) 実開 昭59−145047（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 25/08 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-130553 (JP, A) JP-A-60-94756 (JP, A) Fully open 63-87847 (JP, U) Really open Showa 59- 145047 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 25/08
Claims (2)
する平面形状が大小異なる二つの半導体チップが、前記
各ボンディングパッド群が同一方向を向くとともに露出
し、かつ、両半導体チップ間に複数本のリードが介在さ
れた状態で重ね合わされており、前記各リードと前記各
ボンディングパッドとが各ワイヤによって電気的に接続
されていることを特徴とする半導体装置。1. Two semiconductor chips having a plurality of bonding pads on one principal surface and differing in plane shape in size are exposed while the respective bonding pad groups face the same direction, and a plurality of semiconductor chips are provided between the two semiconductor chips. Wherein the respective leads and the respective bonding pads are electrically connected by respective wires.
には絶縁性のフィルムがそれぞれ介在されていることを
特徴とする特許請求の範囲第１項記載の半導体装置。2. The semiconductor device according to claim 1, wherein an insulating film is interposed between said lead group and each of said semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251949A JP2918574B2 (en) | 1989-09-29 | 1989-09-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251949A JP2918574B2 (en) | 1989-09-29 | 1989-09-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03116860A JPH03116860A (en) | 1991-05-17 |
| JP2918574B2 true JP2918574B2 (en) | 1999-07-12 |
Family
ID=17230380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1251949A Expired - Fee Related JP2918574B2 (en) | 1989-09-29 | 1989-09-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2918574B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847448A (en) * | 1990-12-11 | 1998-12-08 | Thomson-Csf | Method and device for interconnecting integrated circuits in three dimensions |
| JP2629461B2 (en) * | 1991-01-28 | 1997-07-09 | 日本電気株式会社 | Resin-sealed semiconductor device |
| FR2688629A1 (en) * | 1992-03-10 | 1993-09-17 | Thomson Csf | Method and device for three-dimensional encapsulation of semiconductor chips |
| JP2686909B2 (en) * | 1994-02-03 | 1997-12-08 | 和正 菅野 | Semiconductor integrated circuit |
| US5615475A (en) * | 1995-01-30 | 1997-04-01 | Staktek Corporation | Method of manufacturing an integrated package having a pair of die on a common lead frame |
| JP3737333B2 (en) | 2000-03-17 | 2006-01-18 | 沖電気工業株式会社 | Semiconductor device |
| US6620651B2 (en) * | 2001-10-23 | 2003-09-16 | National Starch And Chemical Investment Holding Corporation | Adhesive wafers for die attach application |
| JP5275019B2 (en) * | 2008-12-26 | 2013-08-28 | 株式会社東芝 | Semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58130553A (en) * | 1982-01-29 | 1983-08-04 | Toshiba Corp | Semiconductor device |
| JPS59145047U (en) * | 1983-03-17 | 1984-09-28 | 九州日本電気株式会社 | semiconductor equipment |
| JPS6094756A (en) * | 1983-10-29 | 1985-05-27 | Toshiba Corp | Semiconductor device |
| JPS6387847U (en) * | 1986-11-27 | 1988-06-08 |
-
1989
- 1989-09-29 JP JP1251949A patent/JP2918574B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03116860A (en) | 1991-05-17 |
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