JPS6334553B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address/chapter capture circuit of a recording medium playback device, and relates to an output of a detection circuit that extracts a detection signal when an address/chapter identification signal is input, and a shift unit that extracts an identification signal and data. An address of a recording medium playback device that can reduce the number of input ports of a microcomputer by connecting an AND circuit between the terminals of the register and extracting data and a signal indicating switching of the clock signal from the output of the AND circuit. , aims to provide a chapter capture circuit.

FIG. 1 shows a block system diagram of an address/chapter capture circuit of a recording medium reproducing apparatus previously proposed by the present applicant. In the figure, first, switch 1
When the movable contact piece of is connected to the contact point ◯ and the chapter (track number) is to be selected, for example, ``1, 1'' is supplied to the address/chapter selection signal input terminals 2a and 2b, respectively. The address/chapter identification signal, address data, and chapter data reproduced from a rotating information recording medium (hereinafter referred to as a disk) and input to the input terminal 3 are demodulated by a data demodulator 4, and a clock signal from a clock regenerator 5 (data middle A clock signal is written in , which is shifted by a shift register 6 driven by a clock signal (which is regenerated at the time of reproduction), and taken out from terminals . Here, the signal reproduced from the disk is as shown in Figure 2, the 1st to 4th bits are synchronization signals (a to d), and the 5th and 6th bits are an address (address).
Or the address/chapter identification signal (e, f) to identify the chapter, and the 7th bit and subsequent bits are address data or chapter data (g,...)
Subsequently, signals (a' to f', . . . ) similar to the signals having the above configuration are serially recorded. In this embodiment, the address identification signal is "1, 0" and the chapter identification signal is "1, 1".
(That is, in either case, the fifth bit (signal e) is set to be "1"). Note that these synchronization signals, address/chapter identification signals, address data, and chapter data are recorded during the vertical retrace period of the video signal.

Now, from the terminals of the shift register 6, synchronization signals a to d, chapter identification signals e and f ("1, 1")
is taken out, exclusive OR circuit 7
This is activated by the combination of the input signals a and 7b, and a chapter detection signal is taken out from the NOR circuit 8, and the flip-flop 9 is activated. The ready signal is taken out from the terminal 10 by the operation of the flip-flop 9, while the movable contact piece of the switch 1 is connected to the contact point ○ and the shift register 6 is driven by the read clock signal inputted to the terminal 11 and reads the chapter data ( (7th bit onwards) Shift g,... In this case, the reason why the read clock signal from the terminal 11 is used is that the regenerated clock from the clock regenerator 5 is likely to be affected by jitter, etc., so when reading address data or chapter data, an oscillator or the like that is not affected by jitter or the like is used. The read clock signal from The ready signal is a signal that identifies the address or chapter and indicates that the respective signals are ready to be read out (the movable contact piece of the switch 1 has been switched to contact ○○○). in this case,
Even if the address identification signal is taken out from the shift register 6 midway, the exclusive OR circuits 7a, 7
One input of b is "1, 1" to select the chapter.
Exclusive OR circuit 7
a and 7b do not operate, and no output is taken out from the NOR circuit 8.

In this way, when the selected chapter is identified, the movable contact piece of switch 1 is connected to contact point ○○○,
The chapter data is shifted by the shift register 6 and taken out from the data output terminal 12 via the terminal. When all the chapter data is read out, a reset signal is taken out from the reset terminal 13, the flip-flop 9 is reset, and the switch 1 is turned on.
The movable contact piece is connected to contact ○a.

However, in this device, a terminal 10 for taking out a ready signal indicating that the chapter data or address data is ready to be read and a data output terminal 12 for taking out the chapter data or address data are provided separately, so that it is difficult to use a microcomputer. There was a problem that the number of input ports could not be configured.

The present invention solves the above problems, and each embodiment thereof will be described below with reference to FIGS. 3 and 4.

FIG. 3 shows a block system diagram of the first embodiment of the address/chapter import circuit of the recording medium playback device according to the present invention, and the same components as in FIG. 1 are given the same numbers and their explanations are omitted. . In Figure 3, 1
4 is an AND circuit, one input terminal of which is connected to the terminal of the shift register 6, while the other input terminal is connected to the output side of the flip-flop 9, and its output terminal receives the ready signal and the data signal. It is connected to the dual-purpose output terminal 15.
The rest of the structure is the same as that shown in FIG.

For example, when selecting a chapter, "1, 1" is supplied to the terminals 2a and 2b, respectively, similar to that shown in FIG. Similarly to the one shown in FIG. 1, when the chapter identification signal is detected, the signal ``1'' is taken out from the flip-flop 9 by the chapter detection signal from the NOR circuit 8, and the movable contact piece of the switch 1 becomes the contact ○○○. Connected. On the other hand, the terminal of the shift register 6 has a chapter identification signal (the fifth bit is "1").
is taken out, the output of the AND circuit 14 becomes "1" with the output of the flip-flop 9, and a ready signal is taken out from the output terminal 15. This ready signal indicates that the movable contact piece of switch 1 is connected to contact point ◯◯ and ready to read chapter data (signal from the 7th bit onwards).

When the movable contact piece of the switch 1 is connected to the contact ○○, the shift register 6 driven by the read clock signal from the terminal 11, similar to the one in FIG. The data are sequentially read out and sequentially taken out from the output terminal 15 via the AND circuit 14.

When the ready signal is taken out, the output of the terminal of the shift register 6 is taken out from the AND circuit 14 at the next clock, and the output from the terminal of the previous clock (fifth bit) and the next clock (sixth bit) is 1
5, "1, 1" is obtained at the time of chapter, "1, 0" is obtained at address, and this is the control device (not shown).
It is recognized by After recognizing the chapter or address, address data or chapter data starting from the seventh bit is obtained as described above.

On the other hand, when selecting an address, terminals 2a, 2
"1, 0" are supplied to b, respectively. As in the case of the adapter, when the address identification signal is detected, the address detection signal from the NOR circuit 8 causes the signal "1" to be taken out from the flip-flop 9, and the movable contact piece of the switch 1 is connected to the contact point ○○○. . On the other hand, since the address identification signal (fifth bit "1") is taken out from the terminal of the shift register 6, the ready signal is taken out from the terminal 15 as in the case of the chapter. After this, as in the case of the chapter, the terminals of the shift register 6, the AND circuit 14
Address data is sequentially taken out from the terminal 15 via.

That is, in this embodiment, the chapter identification signal "1,
1'' and the address identification signals ``1, 0'' are both initially ``1'' (fifth bit). The ready signal is taken out from the AND circuit 14 only when the chapter data or address data is detected and ready to be read out, and the chapter or address identification signal is taken out correctly.Then, the same AND circuit 14 is used thereafter. The chapter data or address data can be extracted using the following command. This eliminates the need to separately provide a terminal for taking out the ready signal and a terminal for taking out chapter data or address data, as shown in FIG. 1, and a single terminal can be used for both purposes.

FIG. 4 shows a block system diagram of a second embodiment of the circuit of the present invention, and the same components as in FIG. 1 are given the same numbers and their explanations will be omitted. In Figure 4,
One input terminal of the AND circuit 14 is connected to the output side of the flip-flop 9, while the other input terminal is connected to the output side of the exclusive OR circuit 7a. This is the first (5th bit) of the address identification signal and chapter identification signal.
can be applied whether it is "1" or "0", and when a chapter or address is selected and a chapter identification signal or address identification signal is detected, the output of the exclusive OR circuit 7a is always "1".
The levels of the signals applied to the terminals 2a' and 2b' are selected so that . This is easier to handle than the one in FIG. 3 because the beginning of the address identification signal and the chapter identification signal can be applied at any level. Note that the other configurations, operations, and effects are the same as those shown in FIG. 3, so their explanations will be omitted.

As described above, the address/chapter capture circuit of the recording medium reproducing apparatus according to the present invention is supplied with the address/chapter identification signal and the address/chapter selection signal and receives the identification signal corresponding to the selected address or chapter. An AND circuit is connected between the output of the detection circuit that takes out the detection signal and the terminal that takes out the address of the shift register, the chapter identification signal, the address data, and the chapter data, and when the identification signal is detected and the detection signal is used as the clock signal. Since the configuration is such that the signal indicating that the switching circuit that switches has been activated and the address and chapter data are taken out from the output of the AND circuit, there is a terminal that takes out the address data and chapter data, and a terminal that takes out the signal that shows that the switching circuit has been activated. The microcomputer can be configured with fewer terminals than a circuit provided separately, thereby allowing the microcomputer to be configured with fewer input ports, and has features such as being inexpensive and easy to wire.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of the circuit previously proposed by the applicant, FIG. 2 is a diagram schematically showing the structure of the reproduced signal, and FIGS. 3 and 4 are the first diagram of the circuit of the present invention.
and a block system diagram of the second embodiment. 1... Switch, 2a, 2b, 2a', 2b'... Address/chapter selection signal input terminal, 3... Reproduction signal input terminal, 5... Clock regenerator, 6... Shift register, 9... Flip-flop, 11... Readout clock signal input Terminal, 14...AND circuit, 15...Ready signal and data signal output terminal.

Claims (1)

[Claims] 1. A reproducing circuit that reproduces the address, chapter identification signal, address data, and chapter data serially recorded on a recording medium, and a clock signal from a different circuit to reproduce the address, chapter identification signal, address data, and chapter data from the reproducing circuit. a shift register which takes out an address, a chapter identification signal, address data, and chapter data from a predetermined terminal; Address of a recording medium playback device having a detection circuit that takes out a detection signal when an identification signal corresponding to a selected address or chapter is received, and a switching circuit that switches a clock signal that drives the shift register using the detection signal. , in the chapter import circuit, an AND circuit is connected between the output of the detection circuit and a terminal for extracting the address of the shift register, the chapter identification signal and address data, and the chapter data, and a signal indicating that the switching circuit is activated; 1. An address/chapter import circuit for a recording medium reproducing apparatus, characterized in that the address data and chapter data are extracted from the output of the AND circuit.