JPS6333916A - Charge subtracting device - Google Patents

Abstract

PURPOSE:To obtain the result of subtraction of a 1st signal charge from a 2nd signal charge on a 3rd charge transfer channel by feeding back a comparator output to a gate electrode. CONSTITUTION:In impressing a voltage v1 to a noninverting input of a comparator 17 and a voltage v2 to an inverting input, an output of the comparator 17 goes to a high level and the level of the gate arranged on the 3rd transfer channel 21 adjacent to a 2nd diffusion layer goes to a high level. In impressing a high voltage to the gate, a channel potential beneath the gate electrode goes to a high level and electrons in a 1st diffusion layer override the channel potential and goes to adjacent potential well. Since the entire system forms a negative feedback, the stable point is obtained when the potential v1 of the 1st diffusion layer is equal to the potential v2 of the 2nd diffusion layer. The residual electric charge in the 2nd diffusion layer is equal to the electric charge QB in the 1st diffusion layer with v2=v1. Thus, the electric charge flowing from the 2nd diffusion layer to the adjacent potential well is expressed as (QA-QB) and the subtraction between the transferred charges is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a charge region constructed by a semiconductor charge transfer device.
H. Regarding equipment.

The NTSC composite video signal has one horizontal period (IH=63.5
μs) Addition of the delayed signal and the undelayed original signal yields the luminance signal, and subtraction yields the chrominance signal.

The present invention relates to a subtraction device that subtracts transferred signal charges from other signal charges while maintaining the charge format, and can be suitably used, for example, in the above-mentioned applications.

[Conventional technology]

In a semiconductor charge transfer device, as a conventional example of a charge subtraction device, the one described in Japanese Patent Publication No. 58-19166 is known.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology makes it possible to subtract an amount of charge depending on the voltage applied to the gate electrode from the transfer signal charge, but does not consider subtraction between two transfer signal charges.

The problem to be solved by the present invention is to enable subtraction between two transfer signal charges. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a charge subtraction device using a charge transfer device, which can subtract other transferred charges from the transferred charges.

[Means for solving problems]

a first charge transfer channel for transferring a first signal charge; a first diffusion layer for detecting the first signal charge transferred on the first charge transfer channel; and a second charge transfer channel. a second diffusion layer for detecting a second signal charge transferred on the second charge transfer channel; a third charge transfer channel coupled to the second diffusion layer; a gate electrode disposed adjacent to the second diffusion layer on a third charge transfer channel; and a comparator for comparing potentials of the first diffusion layer and the second diffusion layer; By feeding back the comparator output to the gate electrode, the above objective of obtaining the result of subtracting the first signal charge from the second signal charge on the third charge transfer channel is achieved.

[Effect]

The first diffusion layer detects the charge transferred through the first charge transfer channel as a potential. The detection potential v1 is the first
If the capacitance of the diffusion layer is C, and the transferred charge is -Ql (the transferred charge is an electron, so it is given a negative sign), then -Q s /
It becomes C+.

Similarly, the potential Vt obtained by detecting the charges transferred through the second charge transfer channel by the second diffusion layer is
If the capacitance of the diffusion layer is Ct and the transferred charge is -QA, then Q
a/c! becomes.

By designing the shape of the second diffusion layer part to be the same as the shape of the first diffusion layer part, Cz=CI, so v2 is -Q
a/CI. Now Q, >QIl, then v
t<v.

When vl is applied to the positive-phase input of the comparator and v2 is applied to the negative-phase input, the comparator output goes to a high level, causing the gate electrode arranged on the third transfer channel adjacent to the second diffusion layer to go high. do. When a high voltage is applied to the gate electrode, the channel potential under the gate electrode becomes high, and electrons in the first diffusion layer exceed the channel potential and flow into the adjacent potential well.

Since the entire system is in negative feedback, the point where the potential v of the first diffusion layer and the potential v2 of the second diffusion layer become equal becomes a stable point.

At that time, Vg = v, and the residual charge in the second diffusion layer is
It is equal to the charge Q in the first diffusion layer. In other words, the charge flowing out from the second diffusion layer to the adjacent potential well is (QA - Qll
), which means that subtraction between transferred charges has been executed.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is an explanatory diagram showing one embodiment of the present invention, and FIG.
3 is a timing chart of drive pulses in the figure.

FIG. 1(a) is a schematic vertical cross-sectional view of a semiconductor charge transfer device (an embodiment of the present invention) to which the present invention is applied. In the figure, 2 is a P-type semiconductor substrate, and 2 is an N-type semiconductor layer, which forms a charge transfer channel of an embedded charge transfer device. 3 is a layer in which a P-type impurity is mixed into the N-type semiconductor layer 2, and its function is to form a potential barrier and prevent backflow of charges. 4, 5.6 are N-type diffusion layers, 7a
9a, lla, 12a, 14a, and 15a are transfer gate electrodes made of second N polysilicon, respectively.

7b, 8b, and llb to 14b are each made of first N polysilicon, and constitute storage gate electrodes for storing charge. 10b is a charge subtraction control electrode formed of second layer polysilicon.

Reference numeral 16b denotes an electrode formed of second layer polysilicon, and a voltage potential ■ is applied to the N-type diffusion layer 6 and the N-type diffusion layer 5. Second, it is a reset electrode for resetting during the high period of the reset pulse PR.

17 is a comparator with high differential gain, and 18 is a changeover switch. As shown in FIG. 1, each gate electrode has transfer pulses P, P2, and reset pulse PR.
% DC potential VDCI is supplied.

However, the output of the comparator 17 or the ground potential is applied to the charge subtraction control electrode 10b by the changeover switch 18.

A DC potential VRD is applied to the N-type diffusion layer 5 .

The N-type diffusion layer 4 detects the transferred charge transferred from the left side on the charge transfer channel 2 as a potential. The N-type diffusion layer 6 detects the transferred charges transferred from the right side in the drawing on the charge transfer channel 2 as a potential. In the N type diffusion layer 4, like the N type diffusion layer 6,
It is assumed that a reset circuit for resetting the diffusion layer potential to VRD is arranged adjacently.

Its position should be perpendicular to the charge transfer direction, and although it is not shown in FIG. 1(a) because it is difficult to represent it in perspective, the circuit is connected to the N-type diffusion layer 6. Something similar to the reset circuit is good. Further, it is assumed that the N-type diffusion layers 4 and 6 are designed to have the same shape and have the same capacitance.

The changeover switch 18 is set to the B side (earth side) when the transfer pulse P1 shown in FIG. 2 is high, and to the A side when the transfer pulse P1 is low.
(the output side of the comparator 17).

The transfer channel 2 on the right side of the N-type diffusion layer 6 (hereinafter referred to as 19) is the first charge transfer channel 19, N
A transfer channel 2 (hereinafter referred to as 20) on the left side of the type diffusion layer 4 constitutes a second charge transfer channel 20, and a transfer channel 21 on the right thereof constitutes a third charge transfer channel.

In this embodiment, the signal charges transferred on the second charge transfer channel 20 are transferred to the first charge transfer channel 1.
9, the result of subtracting the signal charge transferred on the third
This is what we are trying to obtain on the charge transfer channel 21 of.

FIG. 2 shows an example of a drive pulse waveform. P+ and Pz are transfer pulses, and P is a beam set pulse. The sample and hold pulse P S/H is required in another embodiment (FIG. 3).

FIG. 1(b) to (f) are each time t shown in FIG.
The downward direction of the potential of the transfer channel at l''ts is defined as the positive direction.

Since the transferred charges are electrons, they move in the direction of higher potential, that is, in the downward direction in FIG.

As is already clear, the example of FIG. 1 is an implanted barrier type two-phase drive charge transfer device. An appropriate DC voltage Vt1CI is applied to the gate electrodes 9a and 15a so that the channel potentials have a relative relationship as shown.

Time 1=1. Figure 1 (b) shows the relative diagram of the channel potential at
). At time t1, the transfer pulse P3 and reset pulse PR are high, and the transfer pulse P is low. The changeover switch 18 is a transfer pulse P.

Since it is high, it is assumed that it is connected to the B side.

Transfer, the potential under the gate electrode to which the transfer pulse P is applied is high. Pulse P
The potential under the gate electrode to which 2 is applied becomes low.

The potential of the channel in the layer 3 mixed with P-type impurities (for example, the channel under the gate electrode 8a) is different from the potential of the channel in the layer 3 not mixed with P-type impurities (for example, the channel under the gate electrode 8a).
The potential is lower than that of the lower channel (b).

The signal charges QA transferred through the second charge transfer channel 20 are accumulated under the gate electrode 8b. The signal charge Q8 transferred through the first charge transfer channel 19 is accumulated under the gate electrode 14b.

Since the reset pulses P and I are high in the N-type diffusion layer 6,
It is electrically connected to the N-type diffusion layer 5 and reset to the power supply potential VRfl applied to the N-type diffusion layer 5. Although the reset circuit is not shown, the N-type diffusion layer 4 is similarly reset to VRD.

Since the ground potential is applied to the gate electrode 10b, the channel potential is low, and the N-type diffusion layer 4 and the third transfer channel 21 are electrically isolated.

A relative diagram of the channel potential at time 1=12 shown in FIG. 2 is shown in FIG. 1(c).

In the first transfer channel 19, the signal charge QB' transferred from the right side of FIG. 1(a) is transferred to the potential well below the gate electrode 13b. Charge Q8 under the gate electrode 14b
begins to be transferred to the N-type diffusion layer 6. Reset pulse P
, are low, so the N-type diffusion layer 6 is electrically isolated from the N-type diffusion layer 5.

In the second transfer channel 20, the signal charge QA' transferred from the left side is transferred to the potential well below the gate electrode 7b. The signal charge QA under the gate electrode 8b begins to be transferred to the N-type diffusion layer 4.

Since the transfer pulse P1 is low, the changeover switch 18 is connected to the A side, and the output of the comparator 17 is applied to the charge subtraction control electrode 10b.

If the charge transferred into the N-type diffusion layer 4 is larger than the charge transferred into the N-type diffusion layer 6, the potential of the N-type diffusion layer 4 becomes lower than the potential of the N-type diffusion layer 6, and the output of the comparator output 17 becomes It becomes high, raising the channel potential under the charge subtraction control electrode 10b (decreasing downward in the figure).

Then, the charge in the N-type diffusion layer 4 is transferred to the charge subtraction control electrode 10.
Overcoming the channel potential under b, storage gate electrode 1
It flows out to the third transfer channel 21 below 1b. With such a mechanism, the charge subtraction control electrode 10
b is controlled.

However, in this example, as described above, the purpose is to subtract the signal charge QIl of the first transfer channel 19 from the signal charge QA of the second transfer channel 20, so QA>QB.

Time 1=1. (d) Relative diagram of channel potential at
Shown below. At this time, when the charge transfer is completed, the signal potentials in the N-type diffusion layers 4 and 6 are equal and the amount thereof is QB. The signal charge in the N-type diffusion layer 4 is Q, which means that the charge flowing out below the storage gate electrode 11b is (QA Q
++), which means that charge subtraction has been executed.

Time 1=1. (e) Relative diagram of channel potential at
Shown below. The charge (QA - Ql) from which the charge under the storage gate electrode 11b has been subtracted begins to be transferred under the storage gate electrode 12b.

Relative diagram of channel potential at time 1-1S (f)
Shown below. At this time, the charge (Qa −
Qm) has been completely transferred below the storage gate electrode 12b. Furthermore, the signal charges within the N-type diffusion layer 4.6 are reset.

The above is one cycle of operation.

Such a charge subtraction device can obtain good electrical characteristics when used for luminance and chromaticity separation of television signals.

The reason for this is that the delay time difference between the two signals to be calculated is accurately determined by the clock frequency and the difference in the number of delay stages.

Another embodiment is shown in FIG. 3, and elements having the same reference numerals as in FIG. 1 have the same functions.

The difference from FIG. 1 is that the output of the comparator 17 is applied to the charge subtraction control electrode lOb via a sample and hold switch consisting of an M0S transistor 22. 23 is a voltage hold capacitor. MOS) transistor 22 receives the sample hold pulse Ps/H shown in FIG.
It is assumed that conduction occurs during the period when is high.

In this example, it is assumed that the charge Q transferred through the first transfer channel 19 is a constant amount. That is, this is a case where a constant amount of charge is always subtracted from the charge QA transferred through the second transfer channel 20. In this example, the voltage supplied to the charge subtraction control electrode tab is controlled to be approximately constant. However, it goes without saying that even in the example of FIG. 1, subtraction of constant ffi charges is possible.

This example is suitable for preventing transfer channel saturation due to added charges when configuring an input addition type transversal filter or the like.

The charge transfer device in the above example has an N-type substrate, a buried channel type, an implanted barrier type, a two-phase gate structure,
Although the present invention is based on a two-phase driving method, the present invention is not limited to the above type.

〔Effect of the invention〕

According to the present invention, in a semiconductor charge transfer device, there is an advantage that charge subtraction with a gain of 1 can be performed between one signal charge QA and another delayed signal charge QB. That is,
Perform the subtraction k (Qa Qa ) = Qc to obtain Qc
When trying to obtain a gain of 1 when the coefficient k is 1,
The present invention makes this possible.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing one embodiment of the present invention, FIG. 2 is a timing chart of driving pulses to explain the operation of FIG. 1, and FIG. 3 is an explanatory diagram showing another embodiment of the present invention. , is. Explanation of symbols 4.6... N-type diffusion layer, 10b... Charge subtraction control electrode, 17... Comparator, 19... First transfer channel, 20... Second transfer channel, 21...3rd
Transfer channel Figure 1 Figure 2 Figure 3 F1

Claims (1)

[Claims] 1. A first charge transfer channel for transferring a first signal charge, and a first charge transfer channel for detecting the first signal charge transferred on the first charge transfer channel as a potential. a first diffusion layer, a second charge transfer channel for transferring a second signal charge, and a second charge transfer channel for detecting the second signal charge transferred on the second charge transfer channel as a potential. a third charge transfer channel coupled to the second diffusion layer, and a gate electrode disposed adjacent to the second diffusion layer on the third charge transfer channel;
a comparator that compares the potential detected in the first diffusion layer and the potential detected in the second diffusion layer;
means for applying the comparison result to the gate electrode in synchronization with a charge transfer clock in each of the charge transfer channels, and applying the result of subtracting the first signal charge from the second signal charge to the third signal charge. A charge subtraction device characterized in that a charge is obtained on a charge transfer channel.