JPH0686181A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve the accuracy as pilot signals in a solid-state image pickup element having a pilot signal generation means generating the pilot signals for detecting gain of two circuit systems performing processings of the signals from two output parts. CONSTITUTION:In a solid-state image pickup element which is provided with two horizontal registers having dummy bits on the side of a transfer destination and a pilot signal generation means supplying signal electric charge of equal amount as a pilot signal to each horizontal register, makes two signals output simultaneously from each horizontal register via the respective output parts and supplies signal electric charge form the pilot signal generation means to each horizontal register so as to output the pilot signal within a dummy bit output period, the gate electrode 30 of an input gate 27 determining the signal amount in the pilot signal generation means is formed by a common electrode and potential difference A2 for measurement is formed under the gate electrode 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and particularly to 2.
The present invention relates to a solid-state image sensor including one horizontal register and pilot signal generating means for supplying an equal amount of signal charges to each horizontal register as a pilot signal, and correcting the gain of a signal processing unit after an output unit based on the pilot signal.

[0002]

2. Description of the Related Art In a solid-state image pickup device such as a CCD, an all-pixel reading method is known in order to further increase the resolution. In this solid-state imaging device, two horizontal registers are provided in consideration of the frequency of the drive pulse of the horizontal register.
Within H (horizontal period), signal charges of two horizontal lines are simultaneously horizontally transferred and output through the respective output sections.

In this case, in the solid-state image pickup device, since the solid-state image pickup element has two output sections and two circuit systems,
There is a problem that horizontal stripes and flicker occur due to the gain difference between the two circuit systems. In particular, when interlaced reading is performed, signals from the same light receiving element (pixel) are transferred by different horizontal registers in the odd field and the even field and output from different output sections, so that a gain difference between the two horizontal registers is generated. Some things cannot be ignored.

In order to solve this problem, the present applicant has previously proposed a solid-state image sensor capable of controlling the gains of two circuit systems for processing the signals output from the two output sections so as to be the same. .

FIG. 8 shows the solid-state image pickup device. In the figure, reference numeral 1 denotes an image part, which is a large number (several hundreds of thousands to several millions) of light receiving elements arranged in a matrix and a vertical register having a CCD structure provided corresponding to each vertical column of the light receiving elements. It consists of 2, 2 ,. For the sake of convenience, the light receiving element is not shown and the image register 1 has vertical registers 2, 2, 2.
Showed as if there were only .... Reference numerals 3a and 3b denote first and second horizontal registers having a CCD structure, which are arranged in parallel to each other on the lower side of the image unit 1, and 4 denotes a control gate unit arranged between the two horizontal registers 3a and 3b. Controls transfer of signal charges between the two horizontal registers 3a and 3b. Reference numerals 5, 5, ... Are channel stoppers provided below the control gate portion 4 at a one-pixel pitch.

Reference numeral 6 is a dummy bit portion formed by extending the horizontal registers 3a and 3b from the portion corresponding to the image portion 1 to the transfer destination side. The dummy bit portion 6 is provided for timing correction and the like, and the number of bits depends on the product type. Although different, it is several bits to several tens of bits. Reference numeral 7 denotes a pilot signal injection portion in which the horizontal registers 3a and 3b and the control gate portion 4 are extended from the portion corresponding to the image portion 1 to the side opposite to the dummy bit portion 6 side by substantially the same number of bits as the dummy bit portion 6.

Reference numeral 8 denotes a pilot signal generator for supplying a signal charge to be a pilot signal to the pilot signal injection portion 7. As shown in FIG. 9, an input source region 9, a first input gate 10a, and a second input gate 10a are provided. It comprises an input gate 10b and an injection gate 11. The input source region 9 is the pilot signal injection unit 7 on the screen.
Although it is shown as if they were integrally formed by the same number of bits as in the above, each bit is actually independent and generates a certain amount or more of signal charge at a predetermined timing, specifically, a level equal to or more than a level required as a pilot signal. .

The input gates 10a and 10b receive the transfer pulse and transfer the signal charge as a pilot signal in the input source region 9 to the horizontal registers 3a and 3b. At this time, the amount of the signal charge is regulated to a fixed amount. Play a role in.

That is, as shown in FIG. 11 (corresponding to the cross section taken along the line AA in FIG. 9), the potential difference A ₁ is applied to each gate electrode 20a, 20b of the first and second input gates 10a, 10b. Bias voltages (that is, gate voltages) V ₁ and V ₂ are applied to form the gate electrode 21 of the input source region 9 and the injection gate 11.
The clock pulses φ _S and φ _G synchronized with the horizontal blanking period are applied to each. Reference numeral 22 is a transfer electrode of the horizontal register. Then, the charge amount e of the pilot signal
_P uses the potential balance method, and the potential difference A ₁ under the first and second input gates 10a and 10b is
Weighed in.

Reference numerals 12a and 12b are first and second output sections for converting the signal charges transferred from the first and second horizontal registers 3a and 3b into voltages and outputting the voltages. 13a and 13b are the first and second output sections. First and second CDSs (phase-to-phase double sampling circuit) for removing noise (reset noise) from the signals of the output units 12a and 12b, and 14a and 14b amplify the output signals of the first and second CDSs 13a and 13b. It is an amplifier, and at least one of the amplifiers is capable of gain control.

The output section 12a in the solid-state image pickup device,
The CDS 13a and the amplifier 14a outside the solid-state image sensor constitute a first circuit system, and the output unit 12 in the solid-state image sensor is formed.
b, the CDS 13b outside the solid-state imaging device, and the amplifier 14b constitute a second circuit system.

A reference numeral 15 samples each color signal from the signals output from the amplifiers 14a and 14b, further processes the sampled color signal to process a luminance signal Y and a color difference signal R.
It is a signal processing circuit for making -Y and BY.

Reference numeral 16 is a gain correction circuit, which includes first and second sample and hold circuits 17a and 17b for sampling pilot signals from the output signals of the first and second amplifiers 14a and 14b, and the first and second sample and hold circuits. It comprises a comparison circuit 18 for comparing the sample and hold circuits. This comparison circuit 1
The output signal of 8 is input as a gain control signal to one amplifier (gain controllable amplifier), for example, the amplifier 14a. The gain control signal becomes, for example, a high level when the level of the pilot signal sampled from the output signal of the first amplifier 14a is lower than the level of the pilot signal sampled from the output signal of the second amplifier 14b. Of the first amplifier 14a.
Reduce the gain of.

A gain control signal may be sent from the comparison circuit 18 to the two output signals having mutually opposite phases to the first and second amplifiers 14a and 14b. In this case, both amplifiers 14a and 14b need to be able to control the gain. When the level of the pilot signal sampled from the output signal of the first amplifier 14a is lower than the level of the pilot signal sampled from the output signal of the second amplifier 14b, the two gain control signals cause the first amplifier 14a While increasing the gain,
The gain of the second amplifier 14b is reduced. In the opposite case, the gain of the first amplifier 14a is reduced and the gain of the second amplifier 14b is increased.

Next, the operation of the above configuration will be described. Figure 10
A is a time chart showing an example of the generation timing of the pilot signal. In this example, a pilot signal is generated every horizontal period, and in synchronization with the horizontal synchronizing signal HD, in other words, during the blanking period, a certain amount of signal charge e is transferred from the input source region 9 to the horizontal registers 3a and 3b. Input gate 10a using _P as a pilot signal,
Inject by the action of 10b. Then, a pilot signal is generated in the output signal of the solid-state imaging device (there are two output signals, but only one is shown for convenience), with a delay of a little longer than one horizontal period after injection.

This pilot signal is sent to the first output section 12a.
The output signal output from the second output unit 12b
The ones output from are also at the same level. This is because the amount of signal charge transferred from the input source region 9 to the horizontal registers 3a and 3b depends on the input gate 10.
This is because it is defined by a and 10b. The generation timing of the pilot signal in the output signal coincides with that of the dummy bit (however, it is delayed by one horizontal period from the injection), and the length of the pilot signal generation period is equal to the length of the dummy bit period. It is almost the same. This is to prevent a rule change (such as a timing change of each signal in the output signal) of the output signal of the solid-state imaging device from occurring by inserting the pilot signal in the output signal.

The length of the pilot signal generation period (in short, the pulse width of the pilot signal) may be shorter than the length of the dummy bit period. The pilot signal may be generated every vertical cycle as shown in FIG. 10B. In the figure, VD is a vertical cycle signal.

According to such a solid-state image pickup device, two circuit systems (channels), that is, the output section 12a and the CDS are provided.
A circuit system including an amplifier 13a and an amplifier 14a, and an output unit 12
b, the CDS 13b, and the amplifier 14b, if there is a gain difference between the circuit system and the amplifier 14a and 14a
It appears as a level difference of the pilot signal in the output signal of b. Then, this level difference is detected by the comparison circuit 18 that compares the output signals of the sample hold circuits 17a and 17b, and this detection signal controls the gain of one or both of the amplifiers 14a and 14b in the direction of eliminating the level difference. In other words, the gain is controlled so as to eliminate the gain difference between the amplifiers 14a and 14b. Therefore, the circuit state is always maintained so that there is no gain difference between the two circuit systems.

Therefore, the adverse effect caused by the gain difference between the two circuit systems, that is, the occurrence of horizontal stripes and flicker is eliminated. Since the pilot signal is output during the dummy bit output period, there is no risk of adversely affecting the processing of the video signal, and therefore there is no need to change the rule for the output signal.

[0020]

In the solid-state image pickup device of FIGS. 8 and 9, the relationship between the bias voltage V ₂ applied to the second input gate 10b and the charge amount of the signal charge to be the pilot signal is first described. As can be seen from the characteristic diagram of FIG. 7 in which the bias voltage V ₁ of the input gate 10a is used as a parameter, the charge amount increases when the bias voltage V ₂ of the second input gate 10b is increased, and decreases when the bias voltage V ₂ of the second input gate 10b is decreased. The charge amount also depends on the bias voltage V ₁ of the first input gate 10a, and the charge amount decreases when the bias voltage V ₁ of the first input gate 10a is increased, and increases when the bias voltage V ₁ of the first input gate 10a is decreased. Has a characteristic opposite to that of the input gate 10b. Reference numeral 23 shows a change in the signal charge amount due to a change in the bias voltage V ₁ of the first input gate 10a. The absolute value of the change amount of the signal amount with respect to the change amount of the bias voltage hardly changes between the first and second input gates 10a and 10b.

By the way, when the signal charge to be the pilot signal to be output from the first output section 12a is injected into the pilot signal injection section 7, and when the signal charge to be the pilot signal to be output from the second output section 12b is changed. Since other clock pulses (that is, a clock pulse for driving the vertical register 2, a clock pulse for inter-horizontal register transfer, a clock pulse for driving the horizontal register, etc.) are different from those when injected into the pilot signal injection portion 7. In addition, the amount of coupling received by the input gates 10a and 10b differs due to variations in wiring resistance, parasitic capacitance between the wiring and the semiconductor, and the like.

The problem here arises when the amount of coupling from the external or internal clock pulse to the input gate 10a and the input gate 10b is different. This means that the amount of charge of the pilot signal changes when different couplings are applied, compared to when there is no coupling. Therefore, when the signal charges are injected into the pilot signal injection unit 7 of the first and second horizontal registers 3a and 3b with a time difference, the mutual charge amounts are not equal due to the influence of coupling.

In view of the above points, the present invention provides a solid-state image pickup device that is less susceptible to the influence of coupling and that can improve the accuracy as a pilot signal.

[0024]

According to the present invention, two horizontal registers 3a and 3b having dummy bits 6 on the transfer destination side are provided.
And a pilot signal generating means 25 for supplying an equal amount of signal charge as a pilot signal to each horizontal register 3a, 3b.
And each output unit 1 from each horizontal register 3a, 3b.
Two signals are output at the same time via 3a and 13b, and the signal charges from the pilot signal generating means 25 to the horizontal registers 3a and 3b are output so that the pilot signal is output within the dummy bit output period. In the solid-state imaging device to be supplied, the gate electrode 30 of the gate unit 27 that determines the signal amount in the pilot signal generating means 25 is formed by one common electrode, and the potential difference A ₂ for measurement is formed under the gate electrode 30. To configure.

The pilot signal generating means 25 is commonly provided for the two horizontal registers 3a and 3b.

Further, the potential difference A ₂ for measurement can be formed by selective impurity implantation.

Further, the potential difference A ₂ for measurement can be formed by changing the film thickness of the insulating film 39 below the gate electrode 30.

[0028]

In the present invention, the pilot signal generating means 2
The gate electrode 3 of the gate portion 27 that determines the signal amount in 5
By forming 0 with one common electrode and forming the potential difference A ₂ for measurement under the gate electrode 30, the gate portion 27 itself is affected by the coupling.
The potential difference A ₂ itself under the gate portion 27 is hardly affected.

Therefore, the amount of coupling received from another clock pulse is different when the signal charge that is the pilot signal for the first output is injected and when the signal charge that is the pilot signal for the second output is injected. However, the change in the amount of charge is negligibly small, and the accuracy of the pilot signal is improved.

By providing the pilot signal generating means 25 in common for the two horizontal registers 3a and 3b, an equal amount of signal charges can be injected into each horizontal register 3a and 3b.

[0031]

Embodiments of the solid-state image pickup device according to the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of a solid-state image pickup device according to the present invention. In the figure, the configuration other than the configuration of the pilot signal generating means is the same as that in FIG. 8 described above, and is therefore designated by the same reference numeral. That is, 1 is an image part, which is a large number (several hundreds of thousands or more) arranged in a matrix.
(Millions of millions) of light receiving elements and vertical registers 2, 2, ... Of CCD structure provided corresponding to each vertical column of the light receiving elements. For the sake of convenience, the light receiving element is not shown and the image portion 1 is not shown.
Are shown as if there are only vertical registers 2, 2 ,. Reference numerals 3a and 3b denote first and second horizontal registers having a CCD structure, which are arranged in parallel to each other on the lower side of the image unit 1, and 4 denotes a control gate unit arranged between the two horizontal registers 3a and 3b. Controls transfer of signal charges between the two horizontal registers 3a and 3b. 5, 5,
Are channel stoppers provided under the control gate portion 4 at a pitch of one pixel.

Reference numeral 6 is a dummy bit portion formed by extending the horizontal registers 3a and 3b from the portion corresponding to the image portion 1 to the transfer destination side. The dummy bit portion 6 is provided for timing correction and the like, and the number of bits depends on the product type. Although different, it is several bits to several tens of bits. Reference numeral 7 denotes a pilot signal injection portion in which the horizontal registers 3a and 3b and the control gate portion 4 are extended from the portion corresponding to the image portion 1 to the side opposite to the dummy bit portion 6 side by substantially the same number of bits as the dummy bit portion 6.

Reference numeral 25 is a pilot signal generator according to the present invention for supplying signal charges to be a pilot signal to the pilot signal injection portion 7, the details of which will be described later.

Reference numerals 12a and 12b are first and second output portions for converting the signal charges transferred from the first and second horizontal registers 3a and 3b into voltages and outputting the voltages, and 13a and 13b are first and second output portions. First and second CDSs (phase-to-phase double sampling circuit) for removing noise (reset noise) from the signals of the output units 12a and 12b, and 14a and 14b amplify the output signals of the first and second CDSs 13a and 13b. It is an amplifier, and at least one of the amplifiers is capable of gain control.

Then, the output section 12a in the solid-state image pickup device,
The CDS 13a and the amplifier 14a outside the solid-state image sensor constitute a first circuit system, and the output unit 12 in the solid-state image sensor is formed.
b, the CDS 13b outside the solid-state imaging device, and the amplifier 14b constitute a second circuit system.

Numeral 15 samples each color signal from the signals output from the amplifiers 14a and 14b, further processes the sampled color signal to process a luminance signal Y and a color difference signal R.
It is a signal processing circuit for making -Y and BY.

Reference numeral 16 denotes a gain correction circuit, which includes first and second sample and hold circuits 17a and 17b for sampling pilot signals from the output signals of the first and second amplifiers 14a and 14b, and the first and second sample and hold circuits. It comprises a comparison circuit 18 for comparing the sample and hold circuits. This comparison circuit 1
The output signal of 8 is input as a gain control signal to one amplifier (gain controllable amplifier), for example, the amplifier 14a. The gain control signal becomes, for example, a high level when the level of the pilot signal sampled from the output signal of the first amplifier 14a is lower than the level of the pilot signal sampled from the output signal of the second amplifier 14b. Of the first amplifier 14a.
Reduce the gain of.

A gain control signal may be sent to the first and second amplifiers 14a and 14b from the two output signals having mutually opposite phases from the comparison circuit 18. In this case, both amplifiers 14a and 14b need to be able to control the gain. When the level of the pilot signal sampled from the output signal of the first amplifier 14a is lower than the level of the pilot signal sampled from the output signal of the second amplifier 14b, the two gain control signals cause the first amplifier 14a While increasing the gain,
The gain of the second amplifier 14b is reduced. In the opposite case, the gain of the first amplifier 14a is reduced and the gain of the second amplifier 14b is increased.

The operation of the above solid-state image pickup device is the same as that described above, and therefore its explanation is omitted.

Therefore, in this embodiment, the pilot signal generator 25 is, as shown in FIGS. 2 and 3, an input source 26 and a gate electrode 3 formed by one common electrode.
0 and an injection gate 28 having a gate electrode 31. When a fixed bias voltage (so-called gate voltage) V _O is applied to the gate electrode 30 of the input gate 27, it is below the gate electrode 30. The potential difference A ₂ for measurement along the charge injection direction is formed. Clock pulses φ _G and φ _S synchronized with the horizontal blanking period are applied to the injection gate 28 and the input source 26, respectively, as in FIG.

The pilot signal generating section 25 including the input source area 26 is common to the first and second horizontal registers 3a and 3b, and the input source area 26 is the same as that described above in the drawing. Although it is shown as if they are integrally formed by the same number of bits as the injection 7, in reality, each bit is independent, and at a predetermined timing, a certain amount or more, specifically, a signal charge of a level required as a pilot signal or more is generated. Occur.

The potential difference A ₂ for measurement under the input gate 27 can be formed by implanting impurities, for example. For example, in the case of the N-type CCD structure, as shown in FIG. 4, P-type impurities are selectively ion-implanted into the N-type region 33 corresponding to the charge measuring portion 27A of the input gate 27 to form the P ⁻ layer 34. To form a shallow potential, or although not shown, N type impurities are selectively ion-implanted into the N type region 33 corresponding to the charge storage portion 27B of the input gate 27 to form an N ⁺ layer. You may try to deepen the potential here.

Conversely, in the case of the P-type CCD structure, N-type impurities are ion-implanted into the P-type region corresponding to the charge measuring section 27A, or P-type impurities are injected into the charge accumulating section 27B. Do like this.

To form the potential difference A ₂ for measurement under the input gate 27, the potential difference can be formed by changing the film thickness of the gate insulating film under the gate electrode 30. For example, as shown in FIG.
A P-type well region 37 and an N-type buried channel region 38 are formed on an N-type semiconductor substrate 36, and a gate electrode 30 of an input gate 27 is formed on the P-type well region 37 and an N-type buried channel region 38 via a gate insulating film 39 such as an oxide film. In the case of the channel type CCD structure, the charge storage section 27 of the input gate 27
This can be realized by making the insulating film thickness t _{1 of} B thicker than the insulating film t ₂ of the charge measuring unit 27A (t ₁ > t ₂ ). Further, as shown in FIG. 6, for example, the P-type region 4 is formed on the N-type semiconductor substrate 41.
2 is formed, and a gate insulating film 39 made of an oxide film or the like is formed thereon.
In the case of a so-called surface channel type CCD structure in which the gate electrode 30 of the input gate 27 is formed via the gate electrode, the insulating film thickness t ₃ of the charge storage portion 27B of the input gate 27 is set to the opposite of the buried channel type. This can be realized by making the insulating film thickness of the measuring unit 27A thinner than t ₄ (t ₃ <t ₄ ).

According to the above-described embodiment, in the pilot signal generator 25, the gate electrode 30 of the input gate 27 is formed by one common electrode, the gate insulating film thickness is changed, or selective impurities are selected. By injecting the bias voltage V _O to the gate electrode 30, a potential difference A ₂ is formed under the gate electrode 30 so that the input gate 27 and thus another clock pulse (A ₂₎ for the potential difference A ₂ ( The influence of coupling due to the vertical register driving clock pulse, the horizontal register driving clock pulse, the horizontal register transfer clock pulse, etc.) becomes extremely small. That is, the change in the amount of signal charge that becomes the pilot signal with respect to the coupling becomes negligibly small. Therefore, another clock pulse is used at the time of injecting the signal charge that becomes the pilot signal to be output from the first output section 12a and at the time of injecting the signal charge that becomes the pilot signal to be output from the second output section 12b. Even if the amount of coupling received from is different,
The influence on the signal charge amount is reduced, and the accuracy of the pilot signal can be improved.

Further, since the pilot signal generating section 25 is provided in common to the pilot signal injecting section 7 of each of the first and second horizontal registers 3a and 3b, an equal amount is provided to each horizontal register 3a and 3b. Signal charges can be injected.

According to the present invention, in the pilot signal generating means, the amount of signal charges to be a pilot signal is less likely to be affected by coupling by another clock pulse, and the accuracy as a pilot signal can be improved. . Therefore, it is possible to provide this type of solid-state imaging device having high reliability.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a solid-state imaging device having a solid-state imaging element according to the present invention.

FIG. 2 is a plan view showing a main part of a solid-state image sensor according to the present invention.

FIG. 3 is a potential diagram on the line BB of FIG.

FIG. 4 is a sectional view showing an example of a main part according to the present invention.

FIG. 5 is a sectional view showing another example of a main part according to the present invention.

FIG. 6 is a cross-sectional view showing another example of the main part according to the present invention.

FIG. 7 is a graph showing a relationship between a bias voltage of an input gate and a charge amount for a pilot signal.

FIG. 8 is a configuration diagram of a solid-state imaging device having a conventional solid-state imaging device.

FIG. 9 is a plan view of a main part of a conventional solid-state image sensor.

FIG. 10 is a time chart showing an example of a pilot signal generation timing.

FIG. 11 is a potential diagram on the line AA of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 image part 2 vertical register 3a 1st horizontal register 3b 2nd horizontal register 4 control gate 6 dummy bit 7 pilot signal injection part 8,25 pilot signal generating means 9,26 input source 10a, 10b, 27 input gate 11, 28 Injection gate A ₁ , A ₂ Potential difference for measurement

Claims (4)

[Claims] 1. A horizontal transfer register, comprising two horizontal registers having dummy bits, and pilot signal generating means for supplying an equal amount of signal charge to each horizontal register as a pilot signal. Signal is supplied from the pilot signal generating means to each of the horizontal registers so that two signals are simultaneously output via the output section and the pilot signal is output within the dummy bit output period. In the solid-state imaging device described above, the gate electrode of the gate portion that determines the signal amount in the pilot signal generating means is formed by one common electrode, and a potential difference for measurement is formed under the gate electrode. Solid-state image sensor. 2. The solid-state image pickup device according to claim 1, wherein the pilot signal generating means is provided commonly to the two horizontal registers. 3. The solid-state imaging device according to claim 1, wherein the potential difference for measurement is formed by selective impurity implantation. 4. The solid-state imaging device according to claim 1, wherein the potential difference for measurement is formed by changing the film thickness of the insulating film under the gate electrode.