JPH08289204A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE: To correct sensitivity difference between output terminals at the amplifier type solid-state image pickup device provided with plural terminals. CONSTITUTION: This device is provided with plural picture elements 2 arranged in the shape of matrix, first load capacitors 81 connected to vertical signal lines 5 of the respective picture elements 2 for holding signals from the picture elements 2, second load capacitors 82 , to which reference voltages are supplied, output circuits 16A and 16B respectively connected to plural horizontal signal lines 10A and 10B, and plural output terminals tA and tB. When reading the signals from the picture elements 2, the reference voltages are held at the second load capacitors 82 , the held reference voltages are inputted through the respective horizontal signal lines 10A and 10B to the output circuits 16A and 16B, and reference signals for detecting gain difference between the respective output circuits 16A and 16B are outputted from the respective output circuits 16A and 16B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device. More specifically, the present invention relates to a capacitive load operation type amplification type solid-state imaging device having a plurality of output terminals.

[0002]

2. Description of the Related Art In response to a demand for higher resolution of a solid-state image pickup device, development of an internal amplification type solid-state image pickup device for amplifying optical signal charge for each pixel has been advanced. The main components of this internal amplification type solid-state image sensor are electrostatic induction transistors (SI).
Various image pickup device structures such as T), amplification type MOS imager (AMI), charge modulation device (CMD), BASIS using a bipolar transistor in a pixel are known.

The following internal amplification type solid-state image pickup device is one of them. In this amplification type solid-state imaging device, holes (signal charges) obtained by photoelectric conversion are accumulated in a p-type potential well of an n-channel MOS transistor (pixel MOS transistor), and potential fluctuations (that is, A change in the channel current based on the change in the potential of the back gate) is output as a pixel signal.

[0004]

On the other hand, the applicant of the present invention has proposed an internal amplification type solid-state image pickup device of a capacitive load operation system which enables uniform sensitivity, high sensitivity and low power consumption.

FIG. 10 shows an example of a capacitive load operation type internal amplification type solid-state image pickup device having a plurality of output terminals. In this amplification type solid-state imaging device 1, as shown in the figure, a light receiving element that constitutes a plurality of unit pixels (cells), for example, a pixel transistor, in this example, a pixel MOS transistor 2 is arranged in a matrix, and pixels in each row are arranged. The gate of the MOS transistor 2 is connected to the vertical selection line 4 selected by the vertical scanning circuit 3 composed of a shift register or the like, and its drain is the power supply _VDD
, And the source of each column is connected to the vertical signal line 5.

An operating MOS switch 7 is connected to the vertical signal line 5.
A load capacitance element 8 that holds a signal voltage (charge) is connected via. An operation pulse φ _OP is applied to the gate of the operation MOS switch 7. The load capacitance element 8 is a horizontal MOS
It is connected to the drain of the switch 9, and the source of the horizontal MOS switch 9 is connected to the horizontal signal line 10 [10A, 10B].

The horizontal signal line 10 has a plurality of horizontal signal lines 10A and 10B in this example, and the load capacitance element 8 corresponding to the horizontal odd-numbered pixel MOS transistor 2 includes the horizontal MOS switch 9. Through the first horizontal signal line 1
The load capacitance element 8 connected to 0A and corresponding to the horizontal even-numbered pixel MOS transistor 2 is connected to the horizontal MOS switch 9
Is connected to the second horizontal signal line 10B via.

Reference numeral 11 is a horizontal scanning circuit composed of a shift register or the like. The horizontal scanning circuit 11 sequentially supplies horizontal scanning pulse φH to the gate of the horizontal MOS switch 9 connected to the horizontal signal line 10 [10A, 10B]. [ΦH ₁ , ...
... φH _m , φH _{m + 1} , ...] are supplied. In this example, the gates of the two horizontal MOS switches 9 corresponding to the two horizontally adjacent pixel MOS transistors 2 are commonly connected and the same horizontal scanning pulse φH is supplied.

At the output ends of the horizontal signal lines 10A and 10B, an output circuit composed of, for example, an output amplifier, in this example, an inverting amplifier, for example, an operational amplifier 13 using a differential amplifier, a detection capacitance element 14, and a reset switch are used. 15 are connected to the charge detection circuits 16A and 16B.

That is, the horizontal signal lines 10A and 10B are connected to the inverting input terminals of the operational amplifiers 13 of the charge detecting circuits 16A and 16B, respectively, and a predetermined bias voltage V _B is applied to their non-inverting input terminals. The bias voltage V _B is for determining the potentials of the horizontal signal lines 10A and 10B. _A detection capacitor element 14 is connected in parallel to the operational amplifier 13, that is, between the inverting input terminal of the operational amplifier 13 and the output terminals t _A and t _B.
In addition, a reset switch 15 for resetting the horizontal signal lines 10A and 10B and the detection capacitance element 14, for example, a MOS
Transistors are connected in parallel.

In this amplification type solid-state image pickup device 1, a vertical scanning signal (that is, vertical selection pulse) φV [φV ₁ from the vertical scanning circuit 3 is sequentially applied to the selection line 4 of each row during the horizontal blanking period in which the reading operation is performed. , ΦV _n , ΦV _{n + 1} ,
...] is applied, the pixel MOS transistors 2 in each row are sequentially selected, and the operation MOS switch 7 is turned on by the operation pulse φ _OP , so that the pixel MO
The S-transistor 2 and the load capacitance element 8 are brought into conduction, and
From the moment the S switch 7 is turned on, the load capacitance element 8 starts to be charged with the signal voltage, and after the signal voltage is sufficiently stabilized,
When the operation MOS switch 7 is turned off, the signal voltage corresponding to the channel potential corresponding to the signal charge amount (hole amount) accumulated in the pixel MOS transistor 2 is held in the load capacitance element 8.

The signal voltage held in the load capacitance element 8 is
During the horizontal scanning period, the horizontal scanning signal from the horizontal scanning circuit 11 is received.
Signal (that is, horizontal scanning pulse) φH [φH₁・ ・ ・ ‥ φH_m,
φH _{m + 1}, ...], the horizontal MOS switch 9 is sequentially turned on.
By turning on the signal, the signal is converted into electric charges on the horizontal signal lines 10A and 1A.
It flows to 0B. Signals flowing to the horizontal signal lines 10A and 10B
The charge is a charge detection circuit 16 using the operational amplifier 13.
The signal is demodulated as a signal voltage to the detection capacitance elements 14 of A and 16B.
And output terminal t as a video signal_A, T_BIs output to
That is, the pixel MOS transistor 2 corresponding to the horizontal odd number
Video signal of terminal t_AOutput to the horizontal even number
The pixel MOS transistor 2 video signal to_BTo
Is output. Detection Capacitance Element of Charge Detection Circuits 16A and 16B
The child 14 is the water corresponding to the next pixel MOS transistor 2.
Before the flat MOS switch 9 turns on, a reset pulse φ_R
Reset switch 15 by turning on
It

According to this amplification type solid-state image pickup device 1, when the signal voltage is held in the load capacitance element 7, almost no current flows in the vertical signal line, so that the resistance of the vertical signal line 5 is greatly affected. And uniform sensitivity can be obtained. Since the load is the capacitive element 7, there is little variation as in the load MOS transistor, and vertical stripe fixed pattern noise (FPN) is less likely to occur.

Since the channel potential of the pixel MOS transistor 2 becomes the potential held in the load capacitance element 8 as it is, the pixel MOS transistor 2 is formed by using the load MOS transistor.
The sensitivity is higher than that in the case where the transistor is operated in a steady state, that is, in the state where a constant current is applied to the channel. Since a steady current does not flow in the pixel MOS transistor 2, power consumption is reduced.

Further, since it has the two output terminals t _A and t _B , the clock frequency of the horizontal scanning circuit 11 can be halved, and the SN ratio is improved by lowering the frequency characteristic of the charge detection circuits 16A and 16B. be able to.

By the way, in the amplification type solid-state image pickup device 1, the detection gain A of the charge detection circuits 16A and 16B is given by
It is expressed by the formula. That is, in the equivalent circuit of FIG.
The capacitance of the load capacitance element 8 is C _L , and the horizontal signal line 10A (10
The parasitic capacitance of B) is C _B , and the charge detection circuit 16A (16B)
The capacity C _D of the detection capacitor element 14, the gain of the operational amplifier 13 and -G, the load capacitor element 8 held signal voltage V
_sig , the output signal V _{out of} the charge detection circuit 16A (16B)
Then, the detection sensitivity of V _out to V _sig , that is, the detection gain A of the charge detection circuit 16A (16B) is expressed by
It becomes like.

[0017]

[Equation 1]

Therefore, in this type of amplification type solid-state image pickup device having a plurality of output terminals, the detection gain A of each output circuit due to the manufacturing variation of each capacitance element and transistor, in this example, the charge detection circuits 16A and 16B, Due to variations, sensitivity differences occur in pixel signals from the output terminals t _A and t _B. In this case, it is extremely difficult to correct the sensitivity difference because there is nothing other than a video signal that changes from moment to moment as a reference for detecting the detection gain of the charge detection circuits 16A and 16B.

In view of the above points, the present invention provides a solid-state image pickup device capable of correcting the sensitivity difference of the output signal from each output terminal.

[0020]

A solid-state image pickup device according to the present invention is a solid-state image pickup device having a plurality of output terminals,
A second load capacitance element to which a reference voltage is supplied is provided in addition to the first load capacitance element that holds the signal from the pixel, and the reference voltage is held in the second load capacitance element when reading the signal of the pixel. Then, the held reference voltage is input to the output circuit through the respective horizontal signal lines, and each output circuit outputs the reference signal for detecting the gain difference of each output circuit.

A solid-state image pickup device according to the present invention is a solid-state image pickup device having a plurality of output terminals, and is connected to a vertical signal line connected to a load capacitance element for holding a signal from a pixel through a switch means. When the pixel voltage is read, the voltage supply means is connected, the reference voltage from the reference voltage supply means is held in the load capacitance element, and the held reference voltage is input to the output circuit via the horizontal signal line, respectively. A reference signal for detecting the gain difference of each output circuit is output from each output circuit.

[0022]

In the solid-state image pickup device according to the present invention, the reference voltage is held in the second load capacitance element when the signal of the pixel is read, and the output signal corresponding to the held reference voltage is output through each output circuit. By doing so, this output signal can be used as a reference signal for correcting the sensitivity difference between the output terminals.

In the solid-state image pickup device according to the present invention, when the signal of the pixel is read out, the reference voltage from the reference voltage supply means is held in the load capacitance element through the vertical signal line of the pixel and held by each output circuit. By outputting the output signal corresponding to the reference voltage, this output signal can be used as a reference signal for correcting the sensitivity difference between the output terminals.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state image pickup device according to the present invention comprises a plurality of pixels arranged in a matrix, a first load capacitance element connected to a vertical signal line of each pixel for holding a signal from the pixel, and a reference voltage. Is supplied to the second load capacitance element, an output circuit connected to each of the plurality of horizontal signal lines, and a plurality of output terminals, and a reference voltage is applied to the second load capacitance element when reading a pixel signal. The holding reference voltage is held and input to the output circuit through the respective horizontal signal lines, and the reference signal for detecting the gain difference of each output circuit is output from each output circuit.

The solid-state imaging device according to the present invention has a plurality of pixels arranged in a matrix, a load capacitance element connected to a vertical signal line of each pixel for holding a signal from the pixel, and a plurality of horizontal signal lines. Each of the output circuits has a plurality of output terminals connected to each other, and the reference voltage supply means is connected to the vertical signal line via the switch means. When the signal of the pixel is read, the reference voltage from the reference voltage supply means is loaded. The capacitor is held, the held reference voltage is input to the output circuit through the respective horizontal signal lines, and each output circuit outputs the reference signal for detecting the gain difference of each output circuit.

The solid-state image pickup device according to the present invention can be configured such that, in the solid-state image pickup device, gain correction means is connected between a plurality of output terminals.

Furthermore, the solid-state image pickup device according to the present invention can be configured to output a reference signal in which the high level and the low level are consecutively output a plurality of times as the reference signal.

An embodiment of a solid-state image pickup device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of a capacitive load operation type internal amplification type solid-state image pickup device having a plurality of output terminals t _A and t _{B according} to the present invention. In FIG. 1, 2
Reference numeral 1 shows the amplification type solid-state imaging device as a whole. Reference numeral 2 denotes a light receiving element that constitutes a unit pixel (cell), for example, a pixel transistor, in this example, a pixel MOS transistor, and a plurality of pixel MOS transistors are arranged in a matrix. Reference numeral 3 is a vertical selection line connected to the gate of the pixel MOS transistor 2 in each row, which is connected to the vertical scanning circuit 3 and is a vertical scanning signal, that is, a vertical scanning pulse φV [φV ₁ , ... φV _n ,
.phi.Vn _{+ 1} , ...] Are sequentially given. The source of the pixel MOS transistor 2 is connected to the vertical signal line 5 for each row,
The drains of all pixel MOS transistors 2 are commonly connected to the power supply V _DD .

A first load capacitance element 8 ₁ for holding a signal from the pixel MOS transistor 2, that is, a signal voltage (charge) is connected to each vertical signal line 5 via an operation MOS switch 7. The load capacitance element 8 ₁ is connected between the vertical signal line 5 and the first potential, which is the ground potential in this example. An operation pulse φ _OP is applied to the gate of the operation MOS switch 7. The load capacitance element 8 ₁ is connected to the drain of a horizontal switch, which is an insulated gate field effect transistor (hereinafter referred to as a horizontal MOS switch) 9 in this example.
The switch source is the horizontal signal line 10 [10A, 10B].
Connected to.

There are a plurality of horizontal signal lines 10, two in this example.
Of the horizontal signal lines 10A and 10B parallel to each other
Load capacitance element corresponding to the th pixel MOS transistor 2
Child 8 ₁Is the first horizontal signal via the horizontal MOS switch 9.
Connected to line 10A and horizontally even pixel MOS transistor
Load capacitance element 8 corresponding to transistor 2₁Is a horizontal MOS switch
It is connected to the second horizontal signal line 10B via the switch 9.

Reference numeral 11 denotes a horizontal scanning circuit composed of a shift register or the like. The horizontal scanning circuit 11 sequentially supplies horizontal scanning pulse φH to the gate of the horizontal MOS switch 9 connected to the horizontal signal line 10 [10A, 10B]. [ΦH ₁ , ...
... φH _m , φH _{m + 1} , ...] are supplied. In this example,
The gates of two horizontal MOS switches 9 corresponding to two horizontally adjacent pixel MOS transistors 2 are commonly connected and the same horizontal scanning pulse φH is supplied.

In this embodiment, in particular, a pilot signal generation circuit for generating a pilot signal necessary for correcting the sensitivity difference between the output terminals t _A and t _{B on} the horizontal signal lines 10A and 10B. 23 is connected.

As shown in the figure, the pilot signal generating circuit 23 includes a vertical signal line 5 and horizontal signal lines 10A and 10A.
Operational MOS connected to B in the same connection relation as described above
Switch 7, the number corresponding to one bit or more bits of the load capacity element 8 ₂ and unit circuit configurations horizontal scanning circuit 11 composed of a horizontal MOS switch 9, four provided the 2 bits in the example, the first half of the A reference voltage supply means (not shown) for supplying a reference voltage for a pilot signal is connected to the two vertical signal lines 5 and the latter two vertical signal lines 5.

That is, instead of the signal voltage from the pixel MOS transistor 2, the reference voltage of the pilot signal is directly applied to the two vertical signal lines 5 in the preceding stage, that is, its low level PS.
Pixel MOS is supplied to the two vertical signal lines 5 in the subsequent stage by supplying _L.
Instead of the signal voltage from the transistor 2 forms to supply a reference voltage of the direct pilot signal, for example, the high-level PS _H.

The load capacitance element 8 ₂ forming the pilot signal generating circuit 23 is called a second load capacitance element in distinction from the _first load capacitance element 8 ₁ which holds the signal voltage from the pixel MOS transistor 2.

The pilot signal generating circuit 23 is connected to the horizontal scanning circuit 11 at the first stage or the last stage, in this example, the last stage, and the two adjacent horizontal MOS transistors at the preceding stage.
A horizontal scanning pulse φH _{M + 1} is applied to the switch 9, and a horizontal scanning pulse φH is applied to two adjacent horizontal MOS switches 9 in the subsequent stage.
_{M + 2} is applied respectively.

At the output terminals of the horizontal signal lines 10A and 10B, for example, an output circuit including an output amplifier, in this example, an inverting amplifier, for example, an operational amplifier 13 using a differential amplifier, a detection capacitance element 14, and a reset switch are used. 15 are connected to the charge detection circuits 16A and 16B.

That is, the horizontal signal lines 10A and 10B are connected to the inverting input terminals of the operational amplifiers 13 of the charge detecting circuits 16A and 16B, respectively, and the predetermined bias voltage V _B is applied to their non-inverting input terminals. The bias voltage V _B is for determining the potentials of the horizontal signal lines 10A and 10B. _A detection capacitor element 14 is connected in parallel to the operational amplifier 13, that is, between the inverting input terminal of the operational amplifier 13 and the output terminals t _A and t _B.
Further, a reset switch 15 for resetting the horizontal signal lines 10A and 10B and the detection capacitance element 14 is connected in parallel.

The reset switch 15 is composed of, for example, a MOS transistor, and its gate has a reset pulse φ.
_R is applied. The operational amplifier 13 is preferably composed of MOS transistors because no current flows.

FIG. 2 is a sectional view showing the semiconductor structure of the unit pixel (that is, pixel MOS transistor) 2. In this figure, 31 is a silicon substrate of the first conductivity type, for example, p type,
Reference numeral 32 denotes a second conductivity type well region of, for example, n type, and 33 denotes a p type well region for accumulating holes (signal charges) 34 photoelectrically converted by receiving light. In this p-type well region 33, n
A source region 35 and a drain region 36 of the mold are formed,
A gate electrode 38G made of, for example, a polycrystalline silicon thin film is formed on both regions 35 and 36 with a gate insulating film 37 interposed therebetween. The holes 34 accumulated by photoelectric conversion in the p-type well region 33 immediately below the gate electrode 38G control the channel current (drain current) during the read operation,
The amount of change in the channel current becomes the signal output. The gate electrode 38G is connected to the vertical selection line 4, and the drain electrode 38G
D is connected to the power supply V _DD , and the source electrode 38S is connected to the vertical signal line 5.

FIG. 3 shows a drive timing chart (vertical synchronization) of the amplification type solid-state image pickup device 21, and FIG. 4 shows a drive timing chart (horizontal synchronization) of the device 21 and an output signal.

In the amplification type solid-state image pickup device 21, the operation MOS switch 7 having the drain connected to the vertical signal line 5 is turned on by the operation pulse φ _OP applied to the gate thereof, and the signal voltage from the pixel MOS transistor 2 is horizontally switched. During the ranking period HBK, the load capacitance element 8 ₁ is read. That is, the signal charge photoelectrically converted by the pixel MOS transistor 2 is amplified to a voltage, output as a signal voltage to the vertical signal line 5, and read out to the load capacitance element 8 ₁ . Load capacitance element 8
_{At 1} , the voltage is held at a potential corresponding to the channel potential corresponding to the amount of signal charges accumulated in each pixel MOS transistor 2, that is, a voltage. Load capacitance element 8
_The signal voltage read to ₁ is output to the horizontal signal lines 10A and 10B by sequentially turning on the horizontal MOS switch 9 scanned by the horizontal scanning circuit 11 during the horizontal video period.

That is, the vertical selection pulse φV [φV ₁ , ... φV _n , ... From the vertical scanning circuit 3 is sequentially applied to the selection line 4 of each row.
.phi.Vn _{+ 1} , ...] Is applied, and the pixel MOS transistors 2 in each row are sequentially selected. For example, during a certain horizontal blanking period, when the potential of the vertical scanning pulse φV _n given to the selection line 4 of the nth row becomes high level, the pixel MO of the nth row is
The S-transistor 2 is turned on and enters the selected state. The potential of the selection line 4 corresponding to non-selection is in the low level state,
The other pixel MOS transistors 2 connected to the selection line 4 are in the non-selected state.

At the same time, when the operation MOS switch 7 is turned on by the operation pulse φ _OP (that is, the high level voltage), the pixel MOS transistor 2 in the nth row is in the operating state, and the signal voltage from the pixel MOS transistor 2 is applied to the load capacitance element 8 Reads to ₁ and operates during the horizontal blanking period.
When the S switch 7 is turned off, that is, when the operation pulse φ _OP returns to the low level voltage and the reading is completed, the signal voltage from the pixel MOS transistor 2 is held in the load capacitance element 8 ₁ . This operation is called capacitive load operation. Immediately after this operation, the substrate pulse φ _sub is applied to the substrate to reset the pixel MOS transistors in the selected row.

On the other hand, similarly to this, in the pilot signal generation circuit 23 as well, instead of the signal voltage from the pixel, the pilot signal reference voltage is held in the load capacitance element 8 ₂ in synchronization with the operation pulse φ _OP for pixel readout. It That is, the previous 2
One of the load capacitor element ₈₂ of the low-level reference voltage PS _L is held, the two load capacitor element ₈₂ in the subsequent stage reference voltage PS _H of high level is maintained.

In this way, the load capacitance element 8₁And 8₂Hold on
The pixel signal for one line of the selected vertical selection line 4 and the pilot signal
The reference signal reference voltage is the horizontal voltage shown in FIG. 1 during the horizontal scanning period.
Horizontal scanning pulse φH [φH from the scanning circuit 11₁‥‥‥
φH_m, ΦH_{m + 1}・ ・ ・ ‥ φH _{M + 1}, ΦH_{M + 2}] By order
By turning on the next horizontal MOS switch 9,
First and second horizontal signal lines 10A and 10 as a load
It flows to B. That is, the horizontal odd-numbered load capacitance element
8₁, 8₂Voltage on the first horizontal signal line 10A
Flat even-numbered load capacitance element 8₁, 8₂Voltage is the second water
Each of them flows as a charge in the flat signal line 10B.

The signal charges flowing out to the respective horizontal signal lines 10A and 10B are the charge detection circuit 1 using the operational amplifier 13.
The signals are demodulated as signal voltages to the detection capacitive elements 14 of 6A and 16B, and the respective signals are output from the output terminals t _A and t _{B of the} charge detection circuits 16A and 16B.

As a result, as shown by the output signal waveform in FIG. 4, the signal (that is, the video signal) 25A from the horizontal odd-numbered pixel MOS transistor 2 is output from the charge detection circuit 16A, and the horizontal even-numbered pixel MOS transistor 2A is output. A signal 25B from 2 (that is, a video signal) is output from the charge detection circuit 16B. At the end of the horizontal scanning period, the low level and the high level of the pilot signals PS ₁ and PS ₂ are output from the charge detection circuits 16A and 16B, respectively.

At this time, there is a gain difference between the charge detection circuits 16A and 16B, and when the respective gains are G ₁ and G ₂ ,
As shown in the output signal waveform of FIG. 4, the difference ΔPS ₁ and ΔPS ₂ between the low level and the high level of the pilot signals of the respective charge detection circuits 16A and 16B is given by the equation (2).

[0051]

[Number 2] charge detection circuit _{16A: ΔPS 1 = G 1 (} PS H -PS L) charge detection circuit _{16B: ΔPS 2 = G 2 (} PS H -PS L)

The sensitivity difference between the output terminals t _A and t _B can be corrected by controlling the gain of an external amplifier (not shown) so that these ΔPS ₁ and ΔPS ₂ match. In FIG. 1, the high level and the low level of the pilot signal are output from the respective charge detection circuits 16A and 16B only once, but by increasing the number of pilot signal generation circuits, as shown in FIG. PS ₁
It is also possible to output the high level and low level of (PS ₂ ) a plurality of times, in this example, three times in succession.

The high level and low level of the pilot signal from each of the charge detection circuits 16A and 16B is at least 1.
As long as the pilot signals are output more than once, the order of outputting the high level and low level pilot signals is arbitrary.

In the embodiment of FIG. 1, the pilot signal is output at the end of each horizontal scanning period, but FIG. 6 is provided with the pilot signal generating circuit of the type that outputs the pilot signal during the vertical blanking period. Another embodiment of the present invention will be described.

In the amplification type solid-state image pickup device 26 of the embodiment shown in FIG. 6, the parts other than the pilot signal generating circuit 27 are the same as those of the embodiment shown in FIG. Overlapping description is omitted. In this example, the pilot signal generating circuit 27 is arranged so as to be located above the imaging region where the pixel MOS transistors 2 are arranged.

That is, this pilot signal generation circuit 27
Is a plurality of switching means for the number of horizontal pixels, for example M
A switching element composed of an OS transistor (hereinafter referred to as MO
S switch) 29, and each MOS switch 29
A common pilot signal generating pulse φPS _OP is applied to the gate of the pilot signal, and its drain is connected to the pilot signal reference voltage supply means for supplying the low level voltage PS _L or the high level voltage PS _H of the pilot signal reference voltage. The source of each MOS switch 29 is connected to the corresponding vertical signal line 5, respectively.

In this example, a low level voltage PS _L is applied to the drains of the MOS switches 29 of every other group, where two MOS switches 29 adjacent to each other in the horizontal direction are grouped, and the other one is set.
Forms to provide a high level voltage PS _H to the drain of a set of MOS switch 29 for every One.

FIG. 7 shows a drive timing chart and output signals of the amplification type solid-state imaging device 26.

In the amplification type solid-state image pickup device 26, as described above, in synchronization with the scanning of the television signal,
The pixel signal of the pixel MOS transistor 2 of one horizontal line selected by the vertical selection line 4 (that is, the high level voltage of the vertical selection pulse φV is applied to the gate of the pixel MOS transistor 2) during the horizontal blanking period is the operating MOS. It is held in the load capacitance element 8 ₁ via the switch 7. The pixel signal for one horizontal line held in the load capacitance element 8 ₁ is
In the horizontal scanning period, the horizontal scanning pulse φH [φH ₁ , ... φH _m , φH _{m + 1} , ...] From the horizontal scanning circuit 11 sequentially turns on the horizontal MOS switch 9, so that the horizontal signal lines 10A and 10B are connected. Is output. That is, for example, the pixel signal of the load capacitance element 8 ₁ corresponding to the horizontal odd-numbered pixel MOS transistor 2 is output to the first horizontal signal line 10A,
The pixel signal of the load capacitance element 8 ₁ corresponding to the horizontal even-numbered pixel MOS transistor 2 is output to the second horizontal signal line 10B, and each pixel signal is the charge detection circuit 16B.
It is output from A and 16B.

[0060] The vertical scanning pulse .phi.V ₁ by this operation the vertical scanning circuit _{3, ‥‥ φV n, φV n} + 1, after up ‥‥ .phi.V _N, the pilot signal generating pulse FaiPS _OP to the next horizontal blanking period each It is applied to the gate of the MOS switch 29. As a result, each MOS switch 29, the drain of which is connected to the high level voltage PS _H or the low level voltage PS _L of the pilot signal reference voltage, turns on and the pilot signal reference voltage is input to each vertical signal line 5. At this time,
Similar to the reading of the pixel MOS transistor 2, the operation MOS switch 7 is turned on by the operation pulse φ _OP to hold the pilot signal reference voltage in the load capacitance element 8 ₁ . Then, during the horizontal scanning period, the pilot signal reference voltage of the horizontal odd-numbered load capacitance element 8 ₁ is output to the first horizontal signal line 10A, and the pilot signal reference voltage of the horizontal even-numbered load capacitance element 8 ₁ is changed to the second pilot signal reference voltage. It is output to the horizontal signal line 10B, and the pilot signal P is output from the charge detection circuits 16A and 16B through the first and second horizontal signal lines 10A and 10B, respectively.
S ₁ and PS ₂ are output. This pilot signal P
Difference between low level and high level of S ₁ and PS ₂ ΔPS ₁ and Δ
PS ₂ is the same as that described in the embodiment of FIG. 1 described above.

The pilot signals PS obtained from the output terminals t _A and t _B as described above are converted into ΔPS ₁ and ΔPS ₂ by the pilot signal detection circuit 32 constituting the gain correction circuit 31 as shown in FIG. Detecting this, gain control amplifier (gain control amplifier) 33 [3
3 ₁ , 33 ₂ ], the gain-corrected output is obtained from the output terminals T ₁ , T ₂ .

[0062] For example, A ^* = K / GCB However gain A ^* is for the input GCB gain control terminal of the gain control amplifier 33, when K has a relationship proportional coefficient, the gain control amplifier 33 ₁ The fixed voltage V _ref is fed back to the gain control terminal as the input GCB ₁ , and the gain control amplifier 3
3 ₂ gain control terminal (ΔPS ₂ −ΔPS ₁ + V _ref )
By feeding back as input GCB ₂ ,
Output signals having no difference in sensitivity can be obtained at the output terminals T ₁ and T ₂ .

A specific example of the gain correction circuit 31 is shown in FIG. In the figure, reference numerals 33 ₁ and 33 ₂ are gain control amplifiers, and charge detection circuits 16A and 16B are connected to their respective inputs.
Output terminals t _A and t _B are connected, and output terminals T ₁ and T ₂ are connected to their respective outputs. The first and second sample and hold circuits 34 and 35 are connected in parallel to the output terminal of the first gain control amplifier 33 _{1, and} the output terminals of the first and second sample and hold circuits 34 and 35 are connected to the differential amplifier 3 respectively.
6 inverting and non-inverting input terminals.

Similarly, the third and fourth sample and hold circuits 39 and 4 are connected to the output terminal of the _second gain control amplifier 33 _2.
0 is connected to the third and fourth sample and hold circuits 3
The output terminals of 9 and 40 are connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 37, respectively. Both differential amplifier 36
The output ends of 37 and 37 are connected to the non-inverting input terminal and the inverting input terminal of the differential amplifier 38, respectively.

On the other hand, the fixed voltage V _ref is supplied to the gain control terminal of the _first gain control amplifier 33 ₁ , and the output from the differential amplifier 38 and the fixed voltage V _ref are added by the analog adder circuit 42. The output is the low-pass filter 43.
Is input to the gain control terminal of the second gain control amplifier 33 ₂ . The low-pass filter 4
3 can also be arranged at the position shown by the broken line.

In this gain correction circuit 31, the first gain control
Amplifier 33₁The gain of A^* ₁, Second gain control amplifier
33₂The gain of A^* ₂Then, the first gain control amplifier
33 ₁Low level A of pilot signal output from^* ₁
(G₁・ PS_L) To the first sample and hold circuit 34
Retained and its high level A^* ₁(G₁・ PS_H) Is second
Of the sample and hold circuit 35. Each sun
Output signal A from the pull-hold circuits 34 and 35
^* ₁(G₁・ PS_L) And A^* ₁(G₁・ PS_H) Is
Each of them is input to the differential amplifier 36 and the difference signal is output from its output end.
A^* ₁{G₁(PS_H-PS_L)} Is output.

On the other hand, the second gain control amplifier 33₂Out of
Low level A of applied pilot signal^* ₂(G₂・ PS
_L) Is held in the third sample hold circuit 39,
High level of^* ₂(G₂・ PS_H) Is the fourth sample
It is held in the field circuit 40. Each sample hold
Output signal A from circuits 39 and 40^* ₂(G₂・ P
S _L) And A^* ₂(G₂・ PS_H) Are differential amplifiers
37 and the difference signal A from its output end.^* ₂{G
₂(PS_H-PS_L)} Is output. This difference signal A^*
₂{G₂(PS_H-PS_L)} And A^* ₂{G₂(PS_H
-PS_L)} Is input to the differential amplifier 38.

[0068] Then, the output signal from the differential amplifier 38 (the so-called difference signal) and a fixed voltage V _{re f} are added are supplied to the respective analog summing circuit 42, the second gain control amplifier whose output is through a low-pass filter 43 By being fed back to the gain control terminal of 33 ₂ , output signals with no difference in sensitivity are obtained from the output terminals T ₁ and T ₂ .

According to the above-described embodiment, in the amplification type solid-state image pickup device having a plurality of output terminals t _A and t _B , the signal indicating the sensitivity difference between the output terminals t _A and t _B , that is, the pilot signal PS [ [PS ₁ , PS ₂ ] can be constantly output during the blanking period.

Then, using this pilot signal, automatic gain correction is performed by the pilot signal detection circuit and the gain correction circuit by the gain control amplifier, so that the sensitivity difference between the outputs of the amplification type solid-state image pickup device having a plurality of output terminals. No adjustment is required to correct

As shown in FIG. 7, as the pilot signals PS ₁ and PS ₂ , when a low level is continuously output a plurality of times and a high level is continuously output a plurality of times, noise, that is, pilot signals Fluctuation components are averaged, and a more accurate pilot signal can be obtained.

In the above example, the pixel MOS transistor is used as the pixel, but it can be applied to a solid-state image pickup device using other pixel transistors such as a pixel bipolar transistor.

[0073]

According to the solid-state image pickup device having a plurality of output terminals according to the present invention, it is possible to output a reference signal indicating a sensitivity difference between outputs.

When the gain correction means is connected to the plurality of output terminals, automatic gain correction between the output terminals is performed, and adjustment for correcting the sensitivity difference between the outputs of the solid-state imaging device having the plurality of output terminals is performed. Can be eliminated.

When a reference signal that outputs a high level and a low level continuously for a plurality of times is used as the reference signal, noise, that is, fluctuation of the reference signal is averaged, and a more accurate reference signal is obtained. can get.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a solid-state imaging device according to the present invention.

FIG. 2 is a sectional view showing a semiconductor structure of a pixel MOS transistor.

FIG. 3 is an operation timing chart (vertical synchronization) of the solid-state imaging device of FIG.

4 is an operation timing chart (horizontal synchronization) of the solid-state imaging device of FIG. 1 and an output signal waveform diagram.

FIG. 5 is a signal waveform diagram showing another example of a pilot signal.

FIG. 6 is a configuration diagram showing another example of the solid-state imaging device according to the present invention.

7A and 7B are an operation timing chart and an output signal waveform chart of the solid-state imaging device of FIG.

FIG. 8 is a configuration diagram of a gain control circuit.

FIG. 9 is a circuit diagram showing a specific example of a gain control circuit.

FIG. 10 is a configuration diagram of a solid-state imaging device according to a comparative example.

FIG. 11 is an equivalent circuit diagram of a charge detection circuit.

[Explanation of symbols]

2 pixel MOS transistor 3 vertical scanning circuit 4 vertical selection line 5 the vertical signal line 7 operation MOS switch 8, 8 _1, 8 ₂ load capacitor element 9 horizontal MOS switches 10, 10A, 10B a horizontal signal line 16A, 16B charge detection circuit t _A , T _B , T ₁ , T ₂ output terminals

Claims (6)

[Claims] 1. A plurality of pixels arranged in a matrix, a first load capacitance element connected to a vertical signal line of each pixel and holding a signal from the pixel, and a second load capacitor to which a reference voltage is supplied. A load capacitance element, an output circuit connected to each of a plurality of horizontal signal lines, and a plurality of output terminals, wherein a reference voltage is held in the second load capacitance element when a signal of the pixel is read, A solid-state imaging device, characterized in that the held reference voltage is input to the output circuit via the respective horizontal signal lines, and a reference signal for detecting a gain difference between the output circuits is output from each output circuit. apparatus. 2. A plurality of pixels arranged in rows and columns, a load capacitance element connected to a vertical signal line of each pixel and holding a signal from the pixel, and an output circuit connected to each of the plurality of horizontal signal lines. A plurality of output terminals, a reference voltage supply means is connected to the vertical signal line via a switching means, and a reference voltage from the reference voltage supply means is applied to the load capacitance element when the signal of the pixel is read. And inputting the held reference voltage to the output circuit via the respective horizontal signal lines, and outputting a reference signal for detecting the gain difference of each output circuit from each output circuit. A characteristic solid-state imaging device. 3. The solid-state image pickup device according to claim 1, wherein gain correction means is connected to the plurality of output terminals. 4. The solid-state imaging device according to claim 2, wherein gain correction means is connected to the plurality of output terminals. 5. The solid-state imaging device according to claim 1, wherein the reference signal is a reference signal in which a high level and a low level are continuously output a plurality of times. 6. The solid-state imaging device according to claim 2, wherein the reference signal is a reference signal in which a high level and a low level are consecutively repeated a plurality of times.