JP2001245221A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device which can obtain signals amplified by an optimum gain, without offset errors. SOLUTION: Plural pixels, plural amplifiers for amplifying and outputting signals form the plural pixels and an offset removing means for removing the offset components of the amplifiers, which are included in signal outputted from the plural amplifiers, are installed in the device. The respective amplifiers have means for varying gains.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having a plurality of amplifiers for amplifying each of signals output from a plurality of pixels.

[0002]

2. Description of the Related Art In recent years, in image input devices such as digital still cameras and digital video cameras, the number of pixels of a sensor has been increased in order to improve the image quality of a captured image. There is a demand for higher speeds. In response to these demands, a scheme has been developed in which a pixel signal is divided into a plurality of read channels and read. This conventional method will be outlined with reference to FIGS.

FIG. 13 is an internal configuration diagram of a conventional solid-state imaging device. The solid-state imaging device shown in FIG. 13 is OB (optical black) arranged two-dimensionally and shielded from light by a light-shielding film or the like.
A plurality of pixels 10 each including a pixel and an effective pixel without a light-shielding film
1, read channels 3071 and 3072 for reading pixel signals and the like from each of the plurality of pixels 101 selected based on the control signal from the vertical scanning circuit 102, and a buffer circuit 119 after being read by the read channels 3071 and 3072. And an output terminal 120 that outputs a pixel signal or the like whose timing has been adjusted by the operation.

The read channels 3071, 30
Reference numeral 72 denotes line memory circuits 104 and 109 for storing pixel signals and the like read from each of the plurality of pixels 101, and pixel signals and the like stored according to horizontal shift pulses input from the input terminals 122 and 123. Readout circuits 106 and 11 including horizontal scanning circuits 105 and 110
1 and amplifiers 107 and 11 for amplifying the read signal
2 and clamping means 124 and 125 for clamping the amplified signal to a predetermined potential.

Next, the operation of the solid-state imaging device shown in FIG. 13 will be described. First, when light is incident on each of the plurality of pixels 101, each of the plurality of pixels 101 generates a pixel signal at a level based on the amount of incident light. Next,
Pixel signals read from the odd-numbered columns of the pixels 101 in the row selected by the vertical scanning circuit 102 are stored in the line memory circuit 104, and then the pixels 1 in the even-numbered columns of the row are read out.
01 is read from the line memory circuit 10
9 is stored.

Subsequently, the horizontal scanning circuit 105 inputs a horizontal shift pulse from outside or inside the chip from an input terminal 122. Then, based on the input horizontal shift pulse, pixel signals read out to the line memory circuit 104 are sequentially selected and output to the amplifier 107. The amplifier 107 amplifies the input pixel signal and outputs it from an output terminal 108 to a processing circuit (not shown).

On the other hand, in the horizontal scanning circuit 110, similarly, pixel signals read out to the line memory circuit 109 are sequentially selected based on the horizontal shift pulse inputted from the input terminal 123, and output to the amplifier 112. Amplifier 1
At 12, the input pixel signal is amplified and output terminal 1
13 to a processing circuit (not shown).

In addition, among the plurality of pixels 101, OB (opt
ical black) The dark level signal output from the pixel is
Clamping is performed to a desired potential using the clamping means 124 and 125. Further, a switch 116 and a switch 1 connected in parallel to the output terminal 108 and the output terminal 113, respectively.
By alternately switching ON / OFF of 17, pixel signals from pixels in odd columns and pixels in even columns are output from the output terminal 120 via the output buffer circuit 119.

At this time, if the potentials clamped by the clamping means 124 and the clamping means 125 are the same, an output signal from which the offset has been removed can be obtained from the output terminal 120.

FIG. 14 shows horizontal shift pulses 1 and 2 input to the input terminals 122 and 123 of FIG. 13, dark level signals and pixel signals output to the output terminals 108 and 113, the switches 116 and 1
17 is a diagram showing an on / off state of No. 17, a dark level signal and a pixel signal output to an output terminal 120, and a clamp pulse for performing a clamp operation. FIG. FIG. 14 shows a state in which a pulse wave of, for example, six clocks is input to the input terminals 122 and 123.

In FIG. 14, among the signals output from the output terminal 120, pixel signals or dark level signals read from pixels in an arbitrary row in the first to twelfth columns are (1) to (12). Number. Output terminal 1
08, the pixel signal at the output terminal 113 includes the output terminal 120
Are assigned numbers corresponding to. (1) to (6) are O
The dark level signal obtained from the B pixel is indicated by (7)-
(12) shows an image signal obtained from an effective pixel.

According to FIG. 14, dark level signals (1), (3), (5) and pixel signals (7), (9), (11) synchronized with the horizontal shift pulse 1 are sequentially sent to the output terminal 108. Dark level signal output and synchronized with horizontal shift pulse 2
(2), (4), (6) and pixel signals (8), (10), (12) are sequentially output to the output terminal 113. Output terminal 10
8. Dark level signal (1) from output terminal 113,
At the time when (2) is output, the clamping means 124,
By operating 125, the dark level signal is clamped to a desired potential.

Subsequently, the switch 116 and the switch 1
By alternately switching ON / OFF of 17, dark level signals (1) to (6) and pixel signals (7) to (12) are sequentially output to the output terminal 120. As described above, since the output terminal 108 and the output terminal 113 need only have a clock rate that is 1/2 of the clock rate of the output terminal 120, the readout time can be relatively easily shortened.

[0014]

However, in the prior art, the gain is not set for each amplifier. For this reason, an offset error exists for each amplifier, and the pixel signal output from the output terminal has a different level depending on the read channel, for example, as shown in FIG. Therefore, the quality of a captured image obtained based on the pixel signal may be degraded.

It is an object of the present invention to provide a solid-state imaging device capable of obtaining a signal amplified with an optimum gain without an offset error.

[0016]

In order to solve the above-mentioned problems, a solid-state imaging device according to the present invention comprises a plurality of pixels; a plurality of amplifiers for amplifying and outputting signals from the plurality of pixels; Offset removing means for removing an offset component of the amplifier included in a signal output from each of the plurality of amplifiers, and each of the amplifiers includes means for varying a gain. And

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic configuration diagram of a pixel and its periphery of a solid-state imaging device according to a first embodiment of the present invention. The solid-state imaging device illustrated in FIG. 1 includes a plurality of pixels 101 having two-dimensionally arranged OB (optical black) pixels that are shielded from light by a light-shielding film or the like and effective pixels without a light-shielding film.
And a vertical scanning circuit 102 for selecting a pixel from which a pixel signal or the like is read from each of the plurality of pixels 101 based on a vertical pulse input from the input terminal 303.

Further, the solid-state imaging device shown in FIG. Buffer circuit 1 read by
19, an output terminal 120 for outputting a pixel signal or the like whose timing is adjusted, and a switch 30 for selecting a read channel 3071 to 3075 for reading the pixel signal or the like.
81 to 3085.

Further, read channels 3071 to 3071
Reference numeral 075 denotes a line memory circuit (not shown) that stores pixel signals and the like read from each of the plurality of pixels 101 and a correlated double sampling (CD) that transfers the stored pixel signals and the like.
S) Readout circuits 3041 to 3045 having circuits and the like
And variable gain amplifiers 3051 to 3055 capable of variably adjusting the gain for amplifying the transferred signal, and clamp means 306 for clamping the amplified signal to a predetermined potential.
1 to 3065.

Next, the operation of the solid-state imaging device shown in FIG. 1 will be described. First, when light is incident on each of the plurality of pixels 101, each of the plurality of pixels 101 generates a pixel signal at a level based on the amount of incident light. The image signals are read out from the readout channels 3071 to 301 connected to each pixel in an arbitrary row selected by the vertical scanning circuit 102.
3075. Vertical scanning circuit 102
Selects the row according to a vertical shift pulse input from outside or inside the chip via the input terminal 303.

The dark level signals obtained from the OB pixels among the two-dimensionally arranged pixels 101 are read out by the read out circuits 3041 to 3045 and then read out from the output terminal 120. The output is output to variable gain amplifiers 3051 to 3055 whose gains are adjusted so that the levels are the same. The variable gain amplifiers 3051 to 3055 amplify the input image signals and output the amplified image signals to the clamp units 3061 to 3065.

In the clamping means 3061 to 3065, the amplified pixel signals and the like are subjected to offset correction, and then output from the output terminal 120 via the switches 3081 to 3085 and the output buffer circuit 119.

FIG. 2 is an internal configuration diagram of the variable gain amplifier 3051 and the clamp means 3061 according to the present embodiment. In the present embodiment, the gain of the variable gain amplifier 3051 is varied based on the output of the buffer circuit 97 and the resistor 98. Note that the variable gain amplifiers 3052 to 3055 and the clamp means 3062 to 30 according to the present embodiment are used.
65 has the same configuration as that of FIG.

In FIG. 2, a variable gain amplifier 3051
Is a positive terminal connected to the power supply 90 and the read circuit 3
An amplifier 93 having a negative terminal connected to the negative terminal 041 via a resistor 91 and an output terminal connected to the negative terminal via a resistor 92 is provided.

The clamp means 3061 is a voltage feedback type clamp means for adjusting the offset amount by feeding back the input dark level signal to the variable gain amplifier 3051 side.
, A transconductance amplifier 94 having a positive terminal connected to the output terminal of the variable gain amplifier 3051, and an output terminal connected to the switch 95. Further, the clamping means 3061
Is, for example, a capacitor 96 connected to the ground and a buffer circuit 9 connected to an amplifier 93 via a resistor 98.
7 is provided.

In the variable gain amplifier 3051 shown in FIG. 2, a dark level signal output from the readout circuit 3041 and a signal fed back from the clamp means 3061 are input, and a signal obtained by adding these signals is amplified. .

Further, the clamp means 3061 turns on the switch 95 before outputting the dark level signal,
Form a negative feedback loop. In this state, the amplified signal from the variable gain amplifier 3051 and the reference voltage of the reference voltage source 504 are input to the transconductance amplifier 94. The transconductance amplifier 94 converts these potential differences into current values and outputs them. Then, the voltage generated in the capacitor 96 is fed back to the variable gain amplifier 3051 via the buffer circuit 97.

Thereafter, when the output signal of the variable gain amplifier 3051 matches the level of the reference voltage of the reference voltage source 504, the negative feedback loop is stabilized. When the negative feedback loop is stabilized, the switch 95 is turned off. When the switch 95 is turned off, by setting the impedance on the output side of each of the clamp means 3061 to be sufficiently high, the offset amount is held as a charge in the capacitor 96 by the clamp operation, and the pixel signal from which the offset has been removed is output. Output from terminal 120.

The structure of the clamp means 3061 to 3065 is not limited to the structure shown in FIG. 2, but may be, for example, a structure shown in FIGS. By the way,
As shown in FIGS. 3 and 4, the clamping means 3061 to 306
5, the variable gain amplifiers 3053-3053
By turning on each switch 805 after inputting the dark level signal from 055, the level of the dark level signal and the reference voltage source 50 are supplied to each coupling capacitor 806.
4 and the level of the reference potential, the electric charge generated is retained. Thereafter, after a predetermined time has elapsed, the switch 805 is turned on.
FF should be used.

In this embodiment, as shown in FIGS. 3 and 4, the clamp means 3061 to 3065 are commonly connected to the reference voltage source 504, and the dark level of the pixel signal is adjusted based on the reference voltage source 504. Clamping. further,
A reference voltage applied to a processing circuit (not shown) connected to the output terminal 120 may be common to the reference voltage source 504.

FIG. 5 shows a vertical shift pulse inputted to the input terminal 303 of FIG. 1, ON / OFF states of the switches 3081 to 3085, a dark level signal and a pixel signal outputted to the output terminal 120, and a clamp for each readout channel. FIG. 4 is a diagram illustrating a clamp pulse for performing an operation. At the rising edge and the falling edge of the vertical shift pulse, the row selected by the vertical scanning circuit 102 is switched, and after the row is selected, the switches 3081 to 3085 are switched.
Are sequentially selected, and a collective pixel signal is output from the output terminal 120.

In FIG. 5, among the signals output from the output terminal 120, those numbered (1) to (5) correspond to the read channels 3071 to 3071, respectively.
The dark level signals read from the OB pixels corresponding to 075 and the signals output from the output terminal 120 and numbered (6) to (10) are read channels 3071 to 3071, respectively. This is a pixel signal read from the pixel corresponding to 3075. When the clamp pulse is at a high level, each clamp means 3061
3065 indicate a state in which a clamping operation is performed.

While the dark level signal is being output to the output terminal 120, the clamp means 3061 to 3065 are operated to clamp the dark level signal.
Therefore, the pixel signals (6) to (10) are output in a state where the offset has been already corrected by the clamp operation.

By arranging OB pixels in each row of the plurality of pixels 101, as shown in FIG.
The period in which 5 is at the high level can be lengthened. Thereby, each read channel 3071 to 30
At 75, the average value of the dark level signals output from the plurality of OB pixels can be clamped to a desired potential.

In this case, for example, uneven dark current is generated in each pixel 101 or each read channel 30
Due to the occurrence of noises of different magnitudes at 71 to 3075, even if the level of the dark level signal output from the output terminal 120 varies every time the vertical shift pulse is switched between the high level and the low level, the noise is not affected. Variation is averaged, and a highly reliable dark level signal can be obtained.

As described above, in this embodiment, since the gains of the variable gain amplifiers 3051 to 3055 are adjusted, the level of the pixel signal output from the output terminal 120 can be made the same. Therefore, for example, each pixel 10
It is known that when a color filter such as R, B, G, etc. is provided in 1, the amount of light transmitted through each color filter differs depending on the wavelength of light from the subject. Since the gain is changed according to the dark level signal from the pixel 101, the level of the output signal output from the output terminal 120 can be made the same.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
FIG. 10 is an internal configuration diagram of a variable gain amplifier 3051 and a clamp means 3061 according to the embodiment. Note that the variable gain amplifiers 3052 to 3055 and the clamp units 3062 to 3065 according to the present embodiment also have the same configuration as in FIG. Further, other parts of the solid-state imaging device of the present embodiment are:
The configuration is the same as that of FIG. Incidentally, the clamp means 3061 is the same as that shown in FIG.

The variable gain amplifier 3051 shown in FIG.
A pixel signal output from each pixel 101 and each pixel 101
And a voltage-current conversion circuit and a current-voltage conversion circuit.

The voltage-current conversion circuit includes a buffer circuit 21 having an input terminal 11 for inputting a pixel signal output from each pixel 101 and connected to an input voltage V _DD1 ,
Input terminal 12 for inputting a noise signal output from 01
And a buffer circuit 22 connected to the input voltage V _DD2 . Buffer circuit 21
The buffer circuit 22, via a resistor R41 are connected, it is converted to a current by the input voltage V _{DD 1,} the differential voltage resistance R41 of the V _DD2.

Further, the current-voltage conversion circuit comprises an amplifier 23
And a resistor R42, and a current mirror circuit CM41, CM42, CM43
The current transmitted by is converted into a voltage again.

According to the present embodiment, even if noise signals of various magnitudes are read from each pixel 101, the noise signal can be removed from the optical signal, so that an image signal which is less affected by the noise signal can be obtained. Obtainable.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
FIG. 10 is an internal configuration diagram of a variable gain amplifier 3051 and a clamp means 3061 according to the embodiment. Note that the variable gain amplifiers 3052 to 3055 and the clamp units 3062 to 3065 according to the present embodiment also have the same configuration as that of FIG. Further, other parts of the solid-state imaging device of the present embodiment are:
The configuration is the same as that of FIG. Incidentally, the clamp means 3061 is the same as that shown in FIG.

The variable gain amplifier 3051 shown in FIG.
A positive terminal for inputting a pixel signal output from each pixel 101 via a resistor 91, a negative terminal for inputting a noise signal output from each pixel 101 via a resistor 99, and a negative terminal via a resistor 92 An amplifier 93 having an output terminal to be connected is provided.

The amplifier 93 amplifies the potential difference between the pixel signal of the pixel 101 input from the positive terminal and the noise signal of the pixel 101 input from the negative terminal according to the adjusted gain, and outputs the amplified signal from the output terminal. ing. For this reason, as in the second embodiment, since a noise signal component can be removed from the optical signal, an image signal that is less affected by the noise signal can be obtained.

(Fourth Embodiment) FIG. 9 shows a fourth embodiment of the present invention.
FIG. 10 is a configuration diagram of a sample hold circuit 807 and clamp means 3062 to 3065 according to the embodiment. In the present embodiment, the clamp unit 3 of the read channel 3071
061 and a signal sampled by the sample hold circuit 807 provided in place of
The reference voltage is ３０3065. The other parts of the solid-state imaging device according to the present embodiment are the same as those in FIG.

The sample and hold circuit 807 shown in FIG.
Before the dark level signal is output, the dark level signal is sampled, and the sampled dark level signal is supplied to the clamp means 3062 to 3065 as a reference voltage. In addition, the sample and hold circuit 807
Since the potentials at the time of clamping of the clamping means 3062 to 3065 are the same, the read channel 3072
3075 operate so as to match the dark level signal of the read channel 3071.

(Fifth Embodiment) FIG. 10 is a configuration diagram of a solid-state imaging device according to a fifth embodiment of the present invention. In the present embodiment, the two read channels 3071 and 3072
For example, a pixel signal from an odd column of the pixels 101 is read by a read channel 3071,
A pixel signal from an even-numbered column of the pixels 101 is read by a read channel 3072.

Therefore, each read channel 307
Read circuits 3041 and 3042 in 1,3072 are:
Line memory circuits 104 and 109 and horizontal scanning circuit 10
5,110. In FIG. 10, the same parts as those in FIG. 1 are denoted by the same reference numerals.

In this embodiment, the variable gain amplifiers 3051 and 3052 and the clamping means 3061 and 306
2 is used in various combinations of those described in the first to third embodiments, but is not limited thereto. For example, as described in the fourth embodiment,
If the sample and hold circuit 807 is used for the clamping means 3061, the clamping accuracy can be improved.

FIG. 11 shows horizontal shift pulses 1 and 2 input to the input terminals 122 and 123 of FIG. 10, dark level signals and pixel signals output to the output terminals 108 and 113, the switches 116 and 1
17 is a diagram showing an on / off state of No. 17, a dark level signal and a pixel signal output to an output terminal 120, and a clamp pulse for performing a clamp operation. FIG. FIG. 11 shows a state in which pulse waves of, for example, six clocks are input to the input terminals 122 and 123.

In FIG. 11, among the signals output from the output terminal 120, pixel signals or dark level signals read from pixels in an arbitrary row in the first to twelfth columns are (1) to (12). Number. Output terminal 1
08, the pixel signal at the output terminal 113 includes the output terminal 120
Are assigned numbers corresponding to. (1) to (6) are O
The dark level signal obtained from the B pixel is shown in (7)-
(12) shows an image signal obtained from an effective pixel.

According to FIG. 11, the dark level signals (1), (3), (5) and the pixel signals (7), (9), (11) synchronized with the horizontal shift pulse 1 are sequentially sent to the output terminal 108. Dark level signal output and synchronized with horizontal shift pulse 2
(2), (4), (6) and pixel signals (8), (10), (12) are sequentially output to the output terminal 113. Output terminal 10
8. Dark level signal (1) from output terminal 113,
At the time when (2) is output, the clamping means 306
By operating 1,3062, the dark level signal is clamped to a desired potential.

Subsequently, the switch 116 and the switch 1
By alternately switching ON / OFF of 17, dark level signals (1) to (6) and pixel signals (7) to (12) are sequentially output to the output terminal 120. As described above, since the output terminal 108 and the output terminal 113 need only have a clock rate that is 1/2 of the clock rate of the output terminal 120, the readout time can be relatively easily shortened.

In this embodiment, since the two read channels 3071 and 3072 are provided, the line memory circuits 104 and 109 may be arranged at a pitch of two pixels. And the line memory circuits 104 and 109 can be easily wired.

As shown in FIG. 12, by increasing the period of the high level of the clamp pulse, a plurality of Os are provided in each of the read channels 3071 to 3075.
The average value of the dark level signal output from the B pixel can be clamped to a desired potential. Therefore, as described with reference to FIG. 6, a highly reliable dark level signal can be obtained.

[0057]

As described above, according to the present invention,
A signal amplified with an optimum gain without an offset error can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a pixel and its periphery of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a variable gain amplifier and a clamp unit of FIG.

FIG. 3 is an internal configuration diagram of a variable gain amplifier and a clamp unit of FIG. 1;

FIG. 4 is an internal configuration diagram of a variable gain amplifier and a clamp unit of FIG. 1;

FIG. 5 is a diagram showing waveforms of the input terminals, switches, and output terminals of the vertical shift pulse shown in FIG. 1 at seven nodes and a clamp pulse for performing a clamp operation for each readout channel.

FIG. 6 is a diagram showing waveforms of seven nodes of an input terminal, each switch, and an output terminal of the vertical shift pulse of FIG. 1 and a clamp pulse for performing a clamp operation for each readout channel.

FIG. 7 is an internal configuration diagram of a variable gain amplifier and a clamp unit according to a second embodiment of the present invention.

FIG. 8 is an internal configuration diagram of a variable gain amplifier and a clamp unit according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram of a sample hold circuit and a clamp unit according to a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram of a solid-state imaging device according to a fifth embodiment of the present invention.

11 is a diagram showing the waveforms of the horizontal shift pulse input terminal, each switch, and the output terminal of the seven nodes of FIG. 10 and a clamp pulse for performing a clamp operation for each read channel.

12 is a diagram showing the waveforms of the input terminals, switches, and output terminals of the seven nodes of the horizontal shift pulse of FIG. 10 and a clamp pulse for performing a clamp operation for each read channel.

FIG. 13 is an internal configuration diagram of a conventional solid-state imaging device.

FIG. 14 is a diagram showing the waveforms of the input terminals, switches, and output terminals of seven nodes of the horizontal shift pulse of FIG. 13 and a clamp pulse for performing a clamp operation for each read channel.

[Explanation of symbols]

 101 pixel 108, 113, 120 output terminal 116, 117, 3081 to 3085 switch 119 buffer circuit 122, 123 input terminal 3041 to 3045 readout circuit 3051 to 3055 variable gain amplifier 3061 to 3065 clamping means 3071 to 3075 readout channel

Claims (15)

[Claims] A plurality of pixels; a plurality of amplifiers for amplifying and outputting signals from the plurality of pixels; and an offset component of the amplifier included in a signal output from each of the plurality of amplifiers. A solid-state imaging device comprising: an offset removing unit for removing; and each of the amplifiers includes a unit for changing a gain. 2. The solid-state imaging device according to claim 1, wherein said offset removing unit includes a clamping unit for clamping a predetermined signal level. 3. The solid-state imaging device according to claim 2, wherein the predetermined signal level includes a dark level signal output from the pixel. 4. The solid-state imaging device according to claim 1, further comprising a plurality of read circuits for reading signals from the plurality of pixels to the plurality of amplifiers. 5. The solid-state device according to claim 2, wherein each of the plurality of amplifiers is configured so that output signals of the plurality of clamp units are fed back. Imaging device. 6. Each of the plurality of amplifiers includes: an input terminal for inputting a pixel signal output from the plurality of pixels and the dark level signal; and a pixel signal input from each of the input terminals. The solid-state imaging device according to any one of claims 3 to 5, further comprising: an output terminal that outputs a difference from the dark level signal. 7. Each of the plurality of amplifiers converts a pixel signal or the dark level signal input from each of the input terminals into a current signal, and converts the converted current signal into a voltage signal. The solid-state imaging device according to claim 6, further comprising a conversion circuit. 8. Each of the plurality of readout circuits includes a shift register for inputting a pixel signal output from the plurality of pixels and the dark level signal to each of the plurality of amplifiers. The solid-state imaging device according to any one of claims 3 to 7, wherein: 9. The solid-state imaging device according to claim 2, wherein said clamp means is provided for each of said plurality of amplifiers, and is connected to a common reference power supply. 10. Each of the plurality of clamp means includes a capacitor for cutting a direct current component of the dark level signal, and a switch having one end connected to the capacitor in parallel. The solid-state imaging device according to claim 9, wherein each of the ends is connected to the reference power supply. 11. The apparatus according to claim 3, wherein the reference power supply includes means for sampling the dark level signal, and wherein each of the plurality of clamping means clamps the sampled dark level signal as a reference. 9. The solid-state imaging device according to any one of items 1 to 8. 12. The solid-state imaging device according to claim 3, wherein the plurality of clamping units clamp an average value of the dark level signal. 13. The solid-state imaging device according to claim 1, wherein the number of the plurality of amplifiers is equal to the number of rows or columns of the plurality of pixels. 14. The solid-state imaging device according to claim 1, wherein each of the plurality of pixels includes a color filter. 15. The pixel signal according to claim 6, wherein each of the plurality of amplifiers amplifies the pixel signal.
The solid-state imaging device according to claim 1.