JP2867655B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A. Industrial application fields B. Summary of the invention C. Prior art [Fig. 4] a. Configuration [Fig. 4] b. Operation D. Problems to be solved by the invention [Fig. 5] E. Problems Means for Solving Points F. Function G. Embodiment [FIGS. 1 to 3] a. Configuration [FIGS. 1 and 2] b. Operation [FIG. 3] H. Effects of the Invention (A The present invention has a solid-state image pickup device, in particular, two horizontal registers provided with dummy bits on a transfer destination side, and outputs two signals from each horizontal register at the same time via an output unit. The present invention relates to a solid-state imaging device.

(B. Summary of the Invention) The present invention provides the above-described solid-state imaging device, which processes signals from two output units of the solid-state imaging device.
In order to add a pilot signal for detecting the gain of the two circuit systems to the video signal without changing the rule regarding signal timing, a dummy bit signal output period (a signal generated by a dummy bit of a horizontal register is output) For convenience, this period is hereinafter referred to as a “dummy bit output period”.
Called. The signal charge is supplied from the pilot signal generation means to each horizontal register so that the pilot signal is output in the parentheses.

(C. Prior Art) [FIG. 4] In a solid-state imaging device such as a CCD, a signal is generally read out by a field read-out method. There is a need to. To read all pixels, it is necessary to read signals of two horizontal lines within 1H (horizontal period).

By the way, in order to read the signals of two horizontal lines within the period of 1H, it is conceivable to set the frequency of the horizontal transfer clock pulse for driving the horizontal register to twice as high as that in the related art. However, this is at least impossible at present.

Therefore, it is conceivable that a plurality of horizontal registers are provided, and the signal charges of the odd-numbered lines and the signal charges of the even-numbered lines are simultaneously horizontally transferred by separate horizontal registers.

(A. Configuration) [FIG. 4] FIG. 4 shows such a solid-state imaging device. In the figure, a is an image portion, a large number of light receiving elements arranged in a matrix, and a vertical register b for vertically transferring signal charges provided corresponding to each vertical column of the light receiving elements, b,... For convenience, a light receiving element is not shown, and a vertical register b,
b,...

c is a first horizontal register disposed below the image section a, d is a second horizontal register spaced slightly below and parallel to the first horizontal register c, and e is the first horizontal register. A control gate disposed between the two horizontal registers cd controls the transfer of signal charges between the first and second horizontal registers cd. f denotes a channel stopper disposed at a position corresponding to one pixel pitch below the control gate e on the surface of the semiconductor substrate, and is indicated by solid color in the figure.

g is a first output unit that extracts and outputs the signal charge transferred from the first horizontal register c, and h is a second output unit that extracts and outputs the signal charge transferred from the second horizontal register d. is there. Here, i is a first CDS circuit (correlated double sampling circuit) for reducing noise of an output signal from the first output unit g, and j is a first CDS circuit for reducing noise of an output signal from the second output unit h. 2 is a first AGC that amplifies the signal of the first CDS circuit i, l is a second AGC that amplifies the signal of the second CDS circuit j, and m is a signal from the AGC k and 1 This is a signal processing circuit that creates a luminance signal Y and color difference signals RY and BY after sampling each color signal.

Although not shown in FIG. 4, the first and second horizontal registers c and d are extended from the portion corresponding to the image portion a to the transfer destination side by several bits or tens of bits to form a dummy bit portion. Has become. The provision of such a dummy bit portion is for timing adjustment and the like.

(B. Operation) Next, the operation will be described.

When the accumulation of the signal charges in each light receiving element is completed, the signal charges of the first line counted from the bottom of the image portion a are transferred in parallel to the first horizontal register c, and further the first gate is controlled by the control gate e. The signal charges on the line are transferred to the second horizontal register d. Next, the signal charges of the second line counted from below the image section a are transferred to the first horizontal register c. Thereafter, the signal charges of the first and second lines are simultaneously transferred by the first and second horizontal registers c and d, and the video signals are simultaneously output from the two output units g and h to the outside of the solid-state imaging device. These operations are repeated every 1H period.

The results of research on a solid-state imaging device having two horizontal registers and outputting two video signals at the same time are introduced in, for example, JP-A-62-92587.

(D. Problems to be Solved by the Invention) [FIG. 5] Meanwhile, in a solid-state imaging device as shown in FIG. 4, a solid-state imaging device has two output units and has two circuit systems. Therefore, there is a problem that horizontal stripes and flicker occur due to a gain difference between the two circuit systems.

In particular, when interlaced reading is performed, signals from the same light receiving element (pixel) are transferred by different horizontal registers c and d in odd fields and even fields and output from different output sections g and h. The fact that there is a gain difference between the registers c and d cannot be ignored. The fact that the signal from the same light receiving element passes through different circuit systems in the odd field and the even field will be described in detail with reference to FIG. 5 as follows.

The figure shows the light receiving elements (B0, A0, B1, A1,
Focusing on the signal charges accumulated in B2 and A2), the flow of the signal charges in the odd field and the even field is compared and shown.

In the odd field, B0 and A0, B1 and A1, B2
And A2 form a pair, and the paired signals are simultaneously read out by the two horizontal registers c and d. Pair 2
The upper A0, A1, A2,... Of the signals of one horizontal line are transferred by the first horizontal register c. The flow of the signal transferred by the first horizontal register c is indicated by a thick arrow. On the other hand, the lower side B0, B1, B2,... Of the signals of the two horizontal lines forming a pair are transferred by the second horizontal register d. The flow of the signal transferred by the second horizontal register d is shown by a thin arrow. It should be noted that thick thin arrows do not indicate differences in signal charge amount and the like.

In contrast, A0 and B1 in the even field
A1 and B2 form a pair, and the paired signals are simultaneously read out by the two horizontal registers c and d. Are transferred by the first horizontal register c, and the lower ones A0, A1,... Are transferred by the second horizontal register d.

Therefore, each light receiving element has a different horizontal register transferred in the odd field or the even field. That is, A0, A1, A2,...
, And the even field is transferred by the second horizontal register d. Also, B
.. Are transferred by the second horizontal register d in odd fields and by the first horizontal register c in even fields.

Therefore, the same signal is processed by different circuit systems (channels) depending on the field. This causes horizontal stripes, flicker, and the like when there is a difference in gain between the two circuit systems.

Of course, even if the problem that the same signal passes through different circuit systems depending on the field is solved by some means, it is not preferable that there is a gain difference between the two circuit systems. Eliminating the gain difference is indispensable in a solid-state imaging device having two output units.

Therefore, the inventors of the present application have conceived of controlling the gains of two circuit systems (channels) for processing signals output from the two output units of the solid-state imaging device so as to be equal. However, to control the gains to be the same, it is necessary to detect the gains of the two circuit systems. Therefore, the inventors of the present application sought a method of detecting the gain of the two circuit systems. As a result, equal amounts of signal charges were injected as pilot signals into the two horizontal registers, and the gain difference between the pilot signals outside the solid-state imaging device. And the idea of controlling the gain of the amplifier in the circuit system based on the detection result of the gain difference so as to eliminate the gain difference was obtained.

However, by inserting a pilot signal into the output signal of the solid-state imaging device, the rule for the timing for defining the output signal must not be changed. Therefore, the inventor of the present application sought a method of inserting a pilot signal without changing a rule regarding an output signal. As shown in FIG. The present invention has been made by focusing on the fact that timing correction can be performed.

That is, the present invention provides a pilot signal for detecting a gain of two circuit systems for processing signals from two output units of a solid-state imaging device without changing a rule regarding signal timing in a video signal. The purpose is to add.

(E. Means for Solving the Problems) In order to solve the above problems, the solid-state imaging device of the present invention has a common input source area and a pilot signal generating means including an input gate area. An equal amount of signal charge generated from the region is used as a pilot signal for the first horizontal register via the input gate, and for the second horizontal register, the input gate, the first horizontal register, The signal charges constituting the pilot signal are supplied from the respective transfer sources via the control gate path, and the first,
The second horizontal register horizontally transfers to the position of the dummy bit on the transfer destination side one horizontal cycle after the supply, and outputs the pilot signal within a dummy bit output period of one horizontal cycle or one vertical cycle. It is characterized by having made it.

(F. Function) According to the solid-state imaging device of the present invention, the dummy bit output period is provided merely for adjusting the timing, and the signal in the period is not a video signal but also a video signal. Not processed. Therefore, if the pilot signal is output during that period, the gain difference between the two circuit systems due to the pilot signal can be detected without changing the rule regarding the timing of the output signal of the solid-state imaging device. Gain control that eliminates the gain difference based on the gain.

(G. Embodiment) [FIGS. 1 to 3] Hereinafter, the solid-state imaging device of the present invention will be described in detail with reference to illustrated embodiments.

1 to 3 are diagrams for explaining one embodiment of the solid-state imaging device of the present invention, and FIG. 1 is a configuration diagram of the solid-state imaging device.

(A. Configuration) [FIGS. 1 and 2] In the drawings, reference numeral 1 denotes an image unit, and a large number (hundreds of thousands to several millions) of light receiving elements arranged on a matrix and each vertical light receiving element .. Are provided corresponding to the columns. It is to be noted that, for convenience, the light receiving elements are not shown, and the image section 1 is shown as if it had only the vertical registers 2, 2,.

3a is a first horizontal register disposed below the image unit 1, 3b is a second horizontal register disposed below and parallel to the first horizontal register 3a at a distance from the first horizontal register 3a. A control gate disposed between the two horizontal registers 3a and 3b controls a signal transfer between the two horizontal registers 3a and 3b. Reference numerals 5, 5,... Denote channel stoppers arranged at a one-pixel pitch at positions below the control gate 4 on the surface of the semiconductor substrate, and are indicated by solid lines in the figure.

Numeral 6 denotes a dummy bit portion obtained by extending the horizontal registers 3a and 3b from the portion corresponding to the image portion 1 to the transfer destination side.
The bit number is provided for timing correction and the like, and the number of bits is several bits to several tens of bits depending on the type.

Reference numeral 7 denotes a pilot signal injection portion in which the horizontal registers 3a and 3b and the control gate 4 are extended from the portion corresponding to the image portion 1 to the side opposite to the dummy bit portion by substantially the same number of bits as the dummy bit portion 6, and 8 denotes the pilot signal injection portion. 7, a pilot signal generator for supplying a signal charge serving as a pilot signal to the input source region 9, as shown in FIG.
It comprises a first input gate 10a and a second input gate 10b.

Although the input source region 9 is shown in the drawing as if it is integrally formed with the same number of bits as the pilot signal injection unit 7, each bit is actually independent, and at a predetermined timing, a predetermined amount or more, specifically, Generates a signal charge higher than the level required as a pilot signal. The input gates 10a and 10b receive the transfer pulse and transfer a signal serving as a pilot signal in the input source region 9 to the horizontal registers 3a and 3b. At this time, the input gates 10a and 10b also serve to regulate the amount of signal charge to a fixed amount. . The generation timing of the pilot signal will be described later in detail.

11a and 11b are first and second output units for converting the signal charges transferred from the first and second horizontal registers 3a and 3b into voltages and outputting the voltages, and 12a and 12b are first and second output units. 11a, 11b
The first and second CDSs (correlated double sampling circuits) 13a and 13b for removing noise (reset noise) from the signal of the first and second CDSs 12a and 12b are amplifiers for amplifying the output signals of at least one of the first and second CDSs 12a and 12b. One of the amplifiers can be controlled in gain. And an output unit in the solid-state imaging device.
11a, CDS 12a outside solid-state image sensor, first by amplifier 13a
Of the solid-state image sensor, the CDS 12b outside the solid-state image sensor, and the amplifier 13b
This forms a second circuit system (second channel).

A signal processing circuit 14 samples each color signal from the signals output from the amplifiers 13a and 13b, and further processes the sampled color signal to generate a luminance signal Y and color difference signals RY and BY.

Reference numeral 15 denotes a gain correction circuit, which includes first and second amplifiers 13a and 13a.
First and second sample-and-hold circuits 16a and 16b for sampling a pilot signal from the output signal of 3b,
And a comparison circuit 17 for comparing the second sample and hold circuit
Consists of The output signal of the comparison circuit 17 is input as a gain control signal to one amplifier (an amplifier capable of gain control), for example, the amplifier 13a. This gain control signal becomes, for example, a high level when the level of the pilot signal sampled from the output signal of the first amplifier 13a is lower than the level of the pilot signal sampled from the output signal of the second amplifier 13b. The gain of the first amplifier 13a is increased to a low level, for example, and the gain of the first amplifier 13a is decreased.

The two output signals having opposite phases from the comparison circuit 17 may be sent to the first and second amplifiers 13a and 13b as gain control signals. In this case, it is necessary that both amplifiers 13a and 13b can control the gain. And the first
When the level of the pilot signal sampled from the output signal of the amplifier 13a is lower than the level of the pilot signal sampled from the output signal of the second amplifier 13b, the gain of the first amplifier 13a is increased by the two gain control signals. At the same time, the gain of the second amplifier 13b is reduced. On the contrary, the gain of the first amplifier 13a is decreased, and the gain of the second amplifier 13b is increased.

(B. Operation) [FIG. 3] FIG. 3 (A) is a time chart showing one example of the generation timing of the pilot signal. In this example, a pilot signal is generated every horizontal cycle, and the horizontal synchronizing signal HD
In other words, during the blanking period, a certain amount of signal charge is supplied from the input source region 9 to the horizontal registers 3a and 3b as pilot signals during the blanking period.
Inject by the action of. Then, the output signal of the solid-state imaging device (there are two output signals, but only one is shown for convenience)
During injection, a pilot signal is generated with a delay slightly longer than one horizontal period. The pilot signal in the output signal output from the first output unit 11a is also included in the second output unit 1a.
The output from 1b also has the same level. This is because the horizontal registers 3a and 3b
The amount of signal charge transferred to the input gates 10a, 10b
Because it is defined by The generation timing of this pilot signal in the output signal matches that of the signal generated by the dummy bit (however, it is delayed by one horizontal period from the injection), and the length of the pilot signal generation period is The length is substantially equal to the length of the dummy bit period. This is to prevent a rule change (such as a change in timing of each signal in the output signal) from occurring in the output signal of the solid-state imaging device by including the pilot signal in the output signal. Note that the length of the generation period of the pilot signal (that is, the pulse width of the pilot signal) may be shorter than the length of the dummy bit output period.

Incidentally, as shown in FIG. 3 (B), the pilot signal may be generated every one vertical cycle. In the figure, VD is a vertical circumference signal.

According to such a solid-state imaging device, there are two circuit systems (channels), that is, a circuit system including the output unit 11a, the CDS 12a, and the amplifier 13a, and a circuit system including the output unit 11b, the CDS 12b, and the amplifier 13a. If there is a gain difference, the difference appears as a level difference between pilot signals in the output signals of the amplifiers 13a and 13b. Then, this level difference is detected by the comparison circuit 17 that compares the output signals of the sample and hold circuits 16a and 16b, and this detection signal controls the gain of one or both of the amplifiers 13a and 13b in a direction to eliminate the level difference. In other words, the gain is controlled so as to eliminate the gain difference between the amplifiers 13a and 13b. Therefore, the circuit state is always maintained so that no gain difference exists between the two circuit systems.

Therefore, the adverse effect caused by the gain difference between the two circuit systems, that is, the occurrence of horizontal stripes and flicker is eliminated.

Since the pilot signal is output during the dummy bit output period, there is no possibility that the processing of the video signal will be adversely affected. Therefore, there is no need to change the rules for the output signal.

(H. Effects of the Invention) As described above, the solid-state imaging device of the present invention includes a first horizontal register having a dummy bit on a transfer destination side, and a second horizontal register having a dummy bit.
Solid-state imaging device having a horizontal register, a control gate formed between the first and second horizontal registers, and simultaneously outputting signals from the first and second horizontal registers via output units, respectively. , A pilot signal generating means comprising a common input source area and an input gate area, and the first horizontal register stores the input gate signal in the first horizontal register as an equal amount of signal charge generated from the common input source area. Via the input gate, the first horizontal register, and the control gate, from the respective transfer sources, and the signal charge forming the pilot signal is supplied to the second horizontal register. The position of the dummy bit on the transfer destination side one horizontal cycle after the supply by the first and second horizontal registers. In horizontally transferred, characterized in that as the pilot signal is output in one horizontal period or within one dummy bit output period for each vertical period.

Therefore, according to the solid-state imaging device of the present invention, the dummy bit output period is provided merely for adjusting the timing, and the signal in that period is not a video signal and is not processed as a video signal. Therefore, if the pilot signal is output during that period, the gain difference between the two circuit systems can be detected by the pilot signal without changing the rule regarding the timing of the output signal of the solid-state imaging device. Gain control that eliminates the gain difference based on the detection result becomes possible.

[Brief description of the drawings]

1 to 3 are diagrams for explaining one embodiment of the solid-state imaging device of the present invention. FIG. 1 is a schematic configuration diagram of a solid-state imaging device, and FIG. 2 is a configuration diagram of a pilot signal generating means. ,
FIGS. 3A and 3B are time charts showing different examples of the generation timing of the pilot signal. FIG. 3A shows an example in which the pilot signal is generated in one horizontal cycle. ) Shows an example in which a pilot signal is generated in one vertical cycle. FIG. 4 is a schematic configuration diagram showing a conventional example of a solid-state imaging device. FIG. 5 is a signal for explaining a problem to be solved by the invention. It is a flowchart of. Description of reference numerals 2 ... vertical register, 3a ... first horizontal register, 3b ...
... Second horizontal register, 6... Dummy bit, 8... Pilot signal generating means, 11a... First output unit, 11b.
A second output unit, 12a ... first CDS, 12b ... second CDS,
13a: first amplifier, 13b: second amplifier, 15: gain correction circuit.

Claims (1)

(57) [Claims] A first horizontal register having a dummy bit on a transfer destination side and a second horizontal register, and a control gate is formed between the first and second horizontal registers; A solid-state imaging device that simultaneously outputs signals from the first and second horizontal registers via an output unit, comprising: a pilot signal generating unit including a common input source region and an input gate region; The same amount of signal charge generated from the above is used as a pilot signal for the first horizontal register via the input gate, and for the second horizontal register, the input gate, the first horizontal register, the control The signal charges forming the pilot signal are supplied to the first and second horizontal registers through the gate paths. One horizontal cycle after the supply, horizontal transfer is performed to the position of the dummy bit on the transfer destination side, so that the pilot signal is output within a dummy bit signal output period of one horizontal cycle or one vertical cycle. A solid-state imaging device characterized by the above-mentioned.