JPS6333739B2 - - Google Patents
Info
- Publication number
- JPS6333739B2 JPS6333739B2 JP55163151A JP16315180A JPS6333739B2 JP S6333739 B2 JPS6333739 B2 JP S6333739B2 JP 55163151 A JP55163151 A JP 55163151A JP 16315180 A JP16315180 A JP 16315180A JP S6333739 B2 JPS6333739 B2 JP S6333739B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- phase
- frequency
- counter
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000010355 oscillation Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 101000736367 Homo sapiens PH and SEC7 domain-containing protein 3 Proteins 0.000 description 2
- 102100036231 PH and SEC7 domain-containing protein 3 Human genes 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55163151A JPS5787241A (en) | 1980-11-18 | 1980-11-18 | Phase synchronizing circuit for optional frequency conversion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55163151A JPS5787241A (en) | 1980-11-18 | 1980-11-18 | Phase synchronizing circuit for optional frequency conversion |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5787241A JPS5787241A (en) | 1982-05-31 |
| JPS6333739B2 true JPS6333739B2 (cs) | 1988-07-06 |
Family
ID=15768186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55163151A Granted JPS5787241A (en) | 1980-11-18 | 1980-11-18 | Phase synchronizing circuit for optional frequency conversion |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5787241A (cs) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07105717B2 (ja) * | 1984-02-10 | 1995-11-13 | 株式会社日立製作所 | クロック発生回路 |
| JPS6346013A (ja) * | 1986-08-13 | 1988-02-26 | Sony Corp | フエ−ズロツクドル−プ回路 |
| JP2549431B2 (ja) * | 1989-02-28 | 1996-10-30 | 富士通株式会社 | ディジタルミキサを含むｐｌｌのデッドロック現象防止回路 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51105751A (en) * | 1975-03-14 | 1976-09-18 | Nippon Electron Optics Lab | Fueizu rotsuku ruupukairo |
-
1980
- 1980-11-18 JP JP55163151A patent/JPS5787241A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51105751A (en) * | 1975-03-14 | 1976-09-18 | Nippon Electron Optics Lab | Fueizu rotsuku ruupukairo |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5787241A (en) | 1982-05-31 |
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