JPS6333377Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to a successive approximation type analog-to-digital converter equipped with a constant current source for range setting. High-resolution analog-to-digital converter (hereinafter referred to as A/D)
An integrated polarization A/D converter is known as a converter. Although the integral type A/D transformer has the advantage of being inexpensive, it is not good at performing high-speed A/D conversion. For that purpose, successive approximation type A/
A D converter is used. However, it takes A/D
The converter is expensive to achieve the same accuracy and resolution as an integrating A/D converter due to the accuracy of the resistor network used therein. Therefore, an object of the present invention is to provide a successive approximation type A/D converter that has a high resolution while having an inexpensive configuration. The A/D converter according to the present invention has a constant current source connected in parallel with a digital-to-analog converter (hereinafter referred to as DAC) in order to expand the conversion range. Hereinafter, the present invention will be explained in detail using the drawings. FIG. 1 is a block diagram showing the entire A/D converter according to one embodiment of the present invention. Input analog signal V _X converted by the A/D converter according to the present invention
is applied to the sample/hold circuit 2 via the switch SW. Sample/hold circuit 2 is connected to a first input of comparator circuit 4 via an input resistor Rin. A second input terminal of the comparator circuit 4 is grounded. The output terminal of the comparison circuit 4 is connected to a well-known successive approximation register (hereinafter referred to as SAR) 6.
As SAR6, for example, a model manufactured by AMD in the United States
Used by connecting two AM2503s in cascade.
That is, after initial setting (all output bits are "0"),
It is well known that only the most significant bit is changed to "1" in synchronization with the clock signal 16, and then the output digital value is raised or lowered in response to the output level of the comparator circuit 4, thereby obtaining the desired digital output. This is a successive approximation register. The upper 2 bits of the digital output terminal of SAR6 are sent to sub DAC8.
The lower 14 bits are connected to the input terminals of the main DAC 10, respectively. Here DAC8 and main DAC
10 functions to absorb an analog current according to an input digital signal. As a sub DAC8,
For example, a 2-bit model DAC08 manufactured by AMD, USA, is used, and a model DAC71 (upper 14 bits out of 16 input bits) manufactured by Burr-Brown, USA is used as the main DAC 10. sub
The output terminals of the DAC 8 and the main DAC 10 are both connected to a common connection point P between the input resistor Rin and the first input terminal of the comparison circuit 4. Further, by switching the switch SW, the input end of the sample/hold circuit 2 is connected to the ramp voltage generation circuit 12. The control circuit 14 is connected to the sample/hold circuit 2, SAR 6, sub DAC 8, and ramp voltage generation circuit 12.
It performs the control action detailed below. For example, the clock signal 16 applied to the SAR 6 is 100k.
Pulses around Hz are used. Although not shown in this figure, a memory for storing the digital output signal of the SAR 6 and a microprocessor for performing various calculations are required. FIG. 2 is a diagram illustrating the conversion range of the A/D transformer shown in FIG. 1. In this figure, the vertical axis on the left side is the sample/hold circuit 2 (see Figure 1).
The arrows indicated by R ₁ to R ₃ indicate the three conversion ranges, and the vertical axis on the right indicates how far each range R ₁ to _{R 3} is from zero potential. (ie, offset voltage). Range R ₁ therefore has an offset voltage of V _a volts, similarly range R ₂ has an offset voltage of V _b volts, and range R ₃ has an offset voltage of V _c volts. Next, offset voltages V _a , V _b , V _c and sub DAC8
(See Figure 1) will be explained. In this embodiment, the sub DAC 8 absorbs three types of constant current. In other words, the sub DAC 8 functions as an offset constant current generating circuit. That is,

[Table] The current is absorbed depending on the input signal. Now, if the resistance value of the input resistor (Rin) is expressed by Rin, it is expressed as follows: V _a = I ₀₁ × (Rin) V _b = I ₀₂ × (Rin) V _c = I ₀₃ × (Rin). (The meaning of offset voltage will be explained below). Note that the offset voltages are selected so that each range appropriately overlaps. Next, the operation of A/D conversion will be explained using FIGS. 1 and 2. Calibration Mode The purpose of calibration mode is to adjust the offset voltages V _a , V _b , V _c of each range (R ₁ , R ₂ , R ₃ ).
It is to measure. During the calibration mode, the switch SW is not turned to the a side, so the input analog signal V _x is isolated from the A/D converter according to the present invention and does not affect the operation. § 1st step Set the input signal of sub DAC8 to "1, 0" (i.e.
Set to range _R1 ). Such settings are performed by the control circuit 14. The control circuit 14 sets the lower 14 bits of SAR6 to "0, . . . 0." Turn the switch SW to the b side and apply the lamp voltage to the input resistor Rin. At this time, sample/
Hold circuit 2 is not activated and the ramp voltage is applied directly to input resistor Rin. When the voltage applied to the comparison circuit 4 (ie, the voltage at point P) reaches zero volts, the output level of the comparison circuit 4 is inverted. In order to hold the input voltage Vin at this time, the control circuit 14 causes the sample/hold circuit 2 to store the Vin. Through the above operations, Vin through which Iin=I ₀₁ flows is determined. This is because the main DAC10 input signal (14
This is because when all bits) are 0, the absorbed current I _M =0. Here, Vin=Iin×(Rin)=I ₀₁ ×(Rin) ∴Vin=V _a (Offset voltage V _a of range R ₁ ) § Second step The holding voltage of the sample/hold circuit 2 is left unchanged. Set the input signal of sub DAC8 to “0, 1” (range
_R2 ). Activate the main DAC 10 and store the obtained 14-bit digital output _v1 in memory (see Figure 2). § Third step Reset the sample/hold circuit 2. The input signal of sub DAC8 is “0, 1” (range
_R2 ). The control circuit 14 sets the lower 14 bits of SAR6 to "0, . . . 0." Apply the lamp voltage to the input resistor Rin, and sample the voltage Vin at the time when the potential at point P becomes zero.
It is held in the hold circuit 2. Due to this,
The Vin through which Iin=I ₀₂ flows is determined. Yotsute Vin＝
V _b (offset voltage of range R ₂ ). § Fourth step The holding voltage of the sample/hold circuit 2 remains unchanged. Set the sub DAC input signal to “0, 0” (range
_R3 ). Activate the main DAC 10 and store the obtained 14-bit digital output _v2 in memory (see Figure 2). § 5th step Turn the switch SW to the C side and set Vin=0. Set the input signal of sub DAC8 to “0, 1” (range
_R2 ). Activate the main DAC 10 and store the obtained 14-bit digital output _v3 in memory (see Figure 2). Offset voltage calculation mode The purpose of this mode is to calculate the offset voltages V _a , V _b , V _c in each range from v ₁ , v ₂ , v ₃ obtained in the calibration mode. That is, the following calculations are performed digitally using a microprocessor. V _a =v ₁ −v ₃ V _b = −v ₃ V _c = −(v ₂ +v ₃ ) Through the above process, the offset voltage in each range is measured. Switch SW in actual A/D conversion mode
is turned to side a. And it is obtained from SAR6.
The range in which this A/D converter is placed is determined from the upper 2 bits of the digital signal (16 bits). Therefore, in order to obtain the true digital conversion value, predetermined offset voltages V _a , V _b ,
V _c is added to the value of the lower 144 bits. for example,
Now, the top two bits obtained from SAR6 are “0,
0'' and the lower 14 bits are D _x , the true digital conversion value will be expressed as [D _x +V _c ]. The accuracy of the A/D converter according to this invention is the main
Depends on DAC10. Furthermore, since the offset voltage is measured using the main DAC 10 as described above, the sub DAC 8 only needs to be stable during the calibration mode. Furthermore, the DC of sample/hold circuit 2
Since the offset is also applied in common throughout the entire process, it cannot become a factor of error. Note that in this embodiment, current-type successive approximation A/
Although only the D converter has been described, the same applies to the voltage type successive approximation A/DD converter. Further, the number of divided ranges can also be arbitrarily set according to the number of bits of the sub-DAC. Since the A/D converter according to the present invention is of the successive approximation type, it is high-speed, and it is possible to substantially expand the conversion range and increase the resolution using an inexpensive DAC. For example, in this embodiment shown in FIG. 1, although a 14-bit main DAC 10 is used,
An A/D converter with substantially 16-bit resolution is realized. Moreover, if monotonicity is guaranteed for all bits of the main DAC 10, monotonicity of the entire A/D converter according to the present invention is also guaranteed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the entire analog-to-digital converter according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating the conversion range of the analog-to-digital converter shown in FIG. 1. 2... Sample/hold circuit, 4... Comparison circuit, 6... Successive approximation register, 8... Sub D/A converter, 10... Main D/A converter, 12... Lamp voltage generation circuit, 14... ...control circuit.

Claims (1)

[Scope of utility model registration request] A successive approximation register, first and second digital-to-analog converters that input the output thereof and output first and second feedback currents for lower digits and upper digits, respectively, an input analog signal and a variable voltage. a sample/hold circuit that selectively inputs the sum of the first and second feedback currents and the sample/hold circuit;
It consists of a comparison circuit that compares signal currents output from the hold circuit via a resistor, and means for inputting the output of the comparison circuit to the successive approximation register,
In calibrating the second feedback current using the first feedback current, the first feedback current is set to a predetermined value, the sample/hold circuit selectively inputs the variable voltage, and calibrates the signal current and the first feedback current. The analog device holds the variable voltage when the second feedback currents are equal in magnitude and have different signs, and the signal current generated by the held variable voltage is calibrated by the first feedback current.・Digital converter.