JPS5871725A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To extend a range of conversion while maintaining highly accurate conversion, by providing a constant current source in parallel to a D/A converter which is provided within a closed loop of a sequential comparator. CONSTITUTION:The upper 2 bits of a sequential comparison register 6 are connected to a sub-D/A converting circuit DAC8; while the lower 14 bits are connected to a main D/A converting circuit DAC10. The DAC8 absorbs three types of constant current in response to the input data. As a result, the offset voltage is generated at an input resistance Rin to shift the analog voltage which is fed to a comparator 4. Thus the range of conversion is increased. Furthermore, the converting accuracy can be maintained at a high level if the converting range is varied since the multiplication is not applied to the input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a successive approximation type analog-to-digital converter equipped with a constant current source for range setting.

An integral type A/D converter is known as a high-resolution analog-to-digital converter (hereinafter referred to as an A/D converter).

Although an integral type A/D converter has the advantage of being inexpensive, it is not good at performing high-speed A/D conversion. For this purpose, a successive approximation type A/D converter is used. However, such A/D converters are expensive due to the accuracy of the resistor network used internally to achieve the same accuracy and resolution as an integrating type, A/D converter.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a successive approximation type A/D converter that is inexpensive but has high resolution.

In order to expand the conversion range, the A/D converter according to the present invention converts the constant current source into a digital-to-analog converter (hereinafter referred to as DAC).
and (5) are connected in parallel.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the entire A/D converter according to an embodiment of the present invention. The input analog signal vx is applied to the sample/hold circuit 2 via the switch SW. Sample/hold circuit 2 is connected to a first input of comparator circuit 4 via an input resistor R-. The second power terminal of the comparison circuit 4 is grounded. The output terminal of the comparison circuit 4 is connected to a well-known successive approximation register (hereinafter referred to as 8AR) 6. As 8AR6,
For example, two model AM 2503 manufactured by American AMD are connected in cascade. That is, after initial setting (all output bits are "0"), only the most significant bit is changed to "1" in synchronization with the clock signal 16, and then the comparator circuit 4
Increase or decrease the output digital value in response to the output level of
This is a well-known successive approximation register. Of the digital output terminals of 5AR6, the upper 2 bits are connected to the sub-DAO8K, and the lower 14 bits are connected to the input terminal of the main DAOIO. Here, the DAC 8 and main DAO 10 function to absorb analog current according to the input digital signal.

As the sub-DAO8, for example, Model D manufactured by AMD in the United States
AOO8 is used as 2 pits, and main DAC10
A model DAC71 (upper 14 bits of 16 input bits) manufactured by Burr-Brown, Inc., USA is used. The output terminals of the sub-DAO 8 and the main DAOIO are both connected to a common connection point P between the input resistor RIin and the first input terminal of the comparison circuit 4. Further, the input terminal of the sample/hold circuit 2 is connected to the ramp voltage generation circuit 12 by the switching K of the switch SW. The control circuit 14 is connected to the sample/hold circuit 2°5AR6, the sub-DAO8, and the ramp voltage generation circuit 12, and performs the control function described in detail below.

As the clock signal 16 applied to the 5AR6, a pulse of around 100 kHz is used, for example. Although not shown in this figure, a memory for storing the digital output signal of the 5AR6 and a microprocessor for performing various calculations are required.

FIG. 2 is a diagram explaining the conversion range of the A/D converter shown in FIG. 1. In this figure, the left vertical axis represents the input voltage Vin stored in the sample/hold circuit 2 (see Figure 1), and the arrows indicated by R1 to R3 represent the three conversion ranges, and the right vertical axis represents the input voltage Vin stored in the sample/hold circuit 2 (see Figure 1). represents how far each range FL, ~R, is from zero potential (i.e., offset voltage). Therefore, range R
, has a va port offset voltage, similarly range R2 has an offset voltage of vb volts, and range R3 has an offset voltage of vc volts.

Next K Off Sera) Voltage va, vb, vc Tosaf DAC
8 (see FIG. 1) will be explained.

In this embodiment, the sub DAC 38 absorbs three types of constant current. In other words, the sub-DAO 8 functions as an offset constant current generation circuit.

That is, current is absorbed depending on the input signal.

Now, if the resistance value of the input resistor Rin is expressed as (Rin), it is expressed as Va=I(11x(Rin)%=I02x(Rin)Vc=I63x(Rin)(The meaning of offset voltage is as follows. (described in F)
. Note that the offset voltages are selected so that each range appropriately overlaps.

Next, the operation of A/D conversion will be explained using FIGS. 1 and 2.

1. Calibration mode The purpose of the calibration mode is to adjust each range (R1
, R2, R3) f)7F 7Se”)) Voltage VB
, vb, and Vc.

Repair 1st step■ Set the input signals of sub-DAO8 to rl and OJ (immediately ζ range Rt). This setting is performed by the control circuit 14. The control circuit 14 sets the lower 14 bits of 5AR6 to "0.....O".

(2) Turn the switch 8W to the (b) side and apply the lamp voltage to the input resistor Rin. At this time, the sample/hold circuit 2 does not operate, and the lamp voltage is directly connected to the input resistor Rin.
is applied to

(2) When the voltage applied to the comparator circuit 4 (that is, the voltage at point P) reaches zero K, the output level of the comparator circuit 4 is inverted. In order to hold the input voltage Vin at this time, the control circuit 14 causes the sample/hold circuit 2 to store the voltage Vin.

By the above operation, Iin = Vin that flows Iol
is determined. Because the main DAOIO input signal (
This is because when all 14 bits) are O, the absorbed current IM=0.

Here Vin = Iin x (Rin) = IoT
X (Rin),'', Vin = Va (offset voltage Va of L/y circuit 1) S 2nd step ■ The holding voltage of the sample/hold circuit 2 is left unchanged.

■ Set the input signal of sub-DAO8 to ro, IJ (range R2).

(2) Activate the main DAC 10 and store the obtained 14-bit digital output v1 in the memory (see Figure 2).

Shadow 3rd step ■Reset sample/hold circuit 2.

■ The input signals of sub-DAO8 are ro, IJ (range R2
).

(2) The control circuit 14 sets the lower 14 bits of 8AR6 to "0.....0".

(2) A ramp voltage is applied to the input resistor Rin, and the voltage Vin at the time when the potential at point P becomes zero is held in the sample/hold circuit 2. From this K, the Vin through which l1n=I, is determined. Therefore, Vin=vb (offset voltage of range island).

Violent IE 4 Step ■ Leave the holding voltage of sample/hold circuit 2 as is.

■ Sub DAC input signal [o, oJ (range ax)]
Set up iC.

(2) Activate the main DAOIO and store the obtained 14-bit digital output v2 in the memory (see Figure 2).

6 5th step ■ Turn down switch SW (QIIK and set Vin = 0.

■ Set the input signal of sub-DAO8 to ro, IJ (range R2).

(2) Activate the main DAC 10 and store the obtained 14-bit digital output v3 in the memory (see Figure 2).

(2) Offset voltage calculation mode The purpose of this mode is to calculate the offset voltages va, vb, and vc in each range from vl * v2 e vl obtained in the calibration mode.

The following operations are performed digitally using a microprocessor.

■V3=vl-vs ■Vb: -V3 ■VC=-(v2+v3) Through the above process, the offset voltage in each range is measured.

In the actual A/D conversion mode, the switch SW is (a1
Defeated by Confucianism. Then, of the digital signal (16 bits) obtained from the 8AR6, it is determined in what range the A/D converter is placed from the upper 2 bits.

Therefore, in order to obtain the true digital conversion value, a predetermined offset voltage vae vb IVc is added to the value of the lower 14 bits. For example, the upper 2 bits obtained from 5AR6 are 0.01, and the lower 14 bits are D.
x, the true digital conversion value is (Dx +V
c) is expressed as K.

The accuracy of the input/D converter according to the present invention is the main DAO10.
Depends on. Also, the offset voltage is the main D as mentioned above.
Since the measurement is performed using the AO 10, the sub-DAO 8 only needs to be stable during the calibration mode.

Furthermore, since the DC offset of the sample/hold circuit 2 is applied in common throughout the entire process, it cannot become a cause of error.

Note that in this embodiment, only the current-type successive approximation A/D converter K was described, but the voltage-type successive approximation A/D converter K.
The same applies to converters. Further, the number of divided ranges can also be arbitrarily set according to the number of pits of the sub-DAC.

Since the A/D converter according to the present invention is a late-blooming comparison type, it is fast, inexpensive, and uses AC (therefore, it can substantially expand the conversion range and increase resolution. For example, FIG. In the present embodiment shown in FIG. 1, an A/D converter with a resolution of 16 bits is realized by using the 14-bit main DAO 10 (despite the difference).Moreover, all bits of the main DAOIO are Oh (hete monotony (MONOTU)
NIOITY ) is guaranteed, A according to the present invention
Monotonicity of the /D converter as a whole is also guaranteed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the entire analog-to-digital converter according to an embodiment of the present invention, and FIG. 142 is a diagram explaining the conversion range of the analog-to-digital converter shown in FIG. 1. 2: Sample/hold circuit, 4: Comparison circuit, 6: Late field comparison register, 8: Sub D/A converter, 10: Main D
/A converter, 12: lamp voltage generation circuit, 14: control circuit. Applicant: Yokogawa Heuret Pats Card Co., Ltd. Agent: Patent attorney Tsugu Hasegawa Otokorok y, rL
Offset turtle pressure F: Ador-2

Claims (1)

[Claims] L An analog-to-digital converter consisting of a successive approximation register, a digital-to-analog converter, and a comparison circuit connected in a closed circuit, which is connected in parallel to the digital-to-analog converter and generates at least two types of constant currents. An analog-to-digital converter characterized by comprising a constant current circuit.