JPS60148227A - Testing method of a/d converter - Google Patents

Abstract

PURPOSE:To attain confirming test while an A/D converter is mounted by applying a signal equivalent to the division of high-order m-bit and low-order n-bit to the A/D converter and comparing its output bit with a reference digital signal. CONSTITUTION:In testing the high-order m-bit of the A/D converter ADC20 to be tested, a control section 11 adds a prescribed bit of the low-order n-bit to the high-order m-bit and applies the result to the DAC20 in order to correct the leakage of error. An analog signal conveted by the DAC12 is inputted to the ADC20 via a switch section 14. The digital signal conerted by the ADC20 is compared with a reference digital signal from the control section 11 at the 1st comparator 15a and the low-order bit is neglected. Then the control section 11 generates a ramp voltage corresponding to the low-order n+1-bit to a test signal generating section 13, this is applied to the ADC20 via a switch section 14, a counter 16 counts incrementally the LSD of the ADC20 and the result is fed to the 2nd comparator 15b. The comparator 15b compares the output of the counter 16 and the converted output of the low-order n-bit of the ADC20.

Description

Detailed Description of the Invention -) Technical Field of the Invention The present invention relates to an A/D converter, particularly an A/D converter installed in a printed distribution board or a completed assembly (hereinafter referred to as a printed board) or a completed assembly. Technology Background Information processing systems have come to be used in a wide range of fields with the development of semiconductor technology, especially integration technology. /D converters and vice versa, D/A converters, have also been made into S product circuits (ICs) and have become available at low cost.0 (c) Prior art and problems Figure 1 shows m + n bits. and \, 8-bit parallel type A
/ D converter C below ADC) block diagram and second
The conversion characteristics are shown in the figure. In the figure, 1 is 256-td
18 encoders, 2I~1. . is a comparator and R is a reference voltage dividing resistor @encoder l has the function of converting 256 human power into a binary code 8 bits 0 Each comparator 2. ~
1.6 is when an analog input signal is applied to each non-inverting input terminal and the analog input signal makes one revolution compared to the target reference voltage Vn obtained by dividing the reference voltage Vref applied to the other inverting input terminal. is each comparator 2. The output voltage at ~us K transitions from a low level O to a high level L ◎The target reference voltage is a constant DC voltage given from the outside, which is divided by resistors to the comparators 21 and 6. 2Wef/! s6・・・・・・255 for comparator 2 Vr @ f /*ss h comparator 2
Since I is given to Vraf in an arithmetic progression, comparators 2. Since each output of the comparator 2 I-@u outputs 1, it corresponds to the voltage 1 of the analog input signal, and as shown in FIG. 2, the reference voltage Vraf/31. 0 obtained at the output terminal of encoder 1 of an 8-bit digital signal with 0 as the minimum scale bit (hereinafter referred to as LSB) In this ADC example, 2' = 2 to obtain 8-bit resolution.
56 comparators2. ~1.6 and this AD
In order to ship C, for example, 11~
Comparative tests have been carried out using a pressure source with an accuracy of 12-bit resolution*. If such an ADC is printed and connected, it can be used as a means of implementing digital processing of detection signals in electrical equipment, etc. In such a case, if it is necessary to test the ADC that has already been incorporated into the printed circuit board, it is difficult to apply a voltage with high precision as described above due to current leakage to peripheral circuits, etc. This voltage source with a low output impedance and a current capacity including leakage current has a problem of being expensive. (d) Object of the Invention The object of the present invention is to eliminate the above-mentioned problems.

Although the accuracy will be slightly lower by dividing the upper bit and lower bit bit, we are trying to provide a means to confirm that the ADC of the test object has the correct operating function by mounting it on the printed board. (e) Structure of the Invention The object of the present invention is to provide a test system in an intermediate or completed packaging unit in which an A/D converter element is mounted and connected together with other additional circuit elements; A D/A conversion means for generating a reference analog voltage by applying a reference digital signal corresponding to the upper m bits of the converter and including the corrected lower bits according to the specifications of the above A/D converter; Ramp voltage generation means for sending out a ramp voltage signal that corresponds to n bits and continuously changes from 0 volts to a maximum voltage comparable to at least n+1 bits, and a reference digital signal to be applied to the output at each upper bit and the D/A conversion means. The control section of the test apparatus includes a first comparing means for comparing, a means for counting the minimum scale bit signal, and a second comparing means for comparing the output of each lower n bit with the output of the counting means. /A converting means to apply each analog reference voltage to the converter, ignoring the lower n bits of the converter, and using the first comparing means to compare and check the output of the upper m bits with the reference digital signal; The lamp voltage generating means is used to apply the full lamp voltage, and the upper m
This is achieved by providing a test method for an A/D converter, characterized in that a second comparing means compares and verifies the output of the lower n bits with the output of the counting means while ignoring the data. I can do it. □ (f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of the A/D converter testing method according to the present invention, and FIG. A block diagram of the second comparing section is shown. In the figure, io is the test device, 20 is the test device
:, ADC to be tested, LL is a control section, 12 is a digital-to-analog converter (DAC), 13 is a test signal generation section, 14 is a switch section, 15a is a first comparison section, 15bri
Second comparison section, 16 is a counter, OR is an OR circuit, ENO
R is an exclusive NOR circuit and AND is an AND circuit.

For example, the control unit 11 is a microprocessor (MPU).
), the ADC 20t of the test object is tested by controlling each of the other components according to a control program and control data stored in a separately provided storage unit (not shown) and control data. Furthermore, since the ADC 20 is mounted on a printed circuit board and connected to the circuit, signal input/output is performed by dipping. It is also assumed that there is a circuit connection to the input terminal, so that no significant voltage is applied even if a small current flows in and out. , and t are each 4 bits, for a total of 8 bits. ◎Of course, any mln can be set.
The AC 12 sends out an analog voltage corresponding to the digital signal applied by the control unit 11.The 0 test signal generating unit 13 continuously changes from 0 volt M according to the clock of the control unit 11, and outputs an analog voltage corresponding to at least n+1 bits. The 0 switch unit 14, which has the function of generating and sending out a ramp voltage or sawtooth wave voltage that reaches a maximum voltage equivalent to 5 bits, is an analog switch using ECL, for example, and the control unit 1
DAC 12 or test signal generator 13 according to the control of
0 first comparison unit 15a that selects the output of and sends it to the ADC 2
The second comparison section 15b has a digital comparison function with a common configuration as shown in Figure @2, and the control section 1
1 applies a comparison timing signal to the first comparison section 15m, and compares and verifies the upper 4 bits 1k.
2.3, which is applied to the comparison unit L5b and removes the LSB from the lower order.
．． Compare and match the 4 bits and test the operation of the lower 4 bits lol
The 0 counter 16 that executes M is an up/down counter with an n-bit capacity that can be preset, and the reset operation is performed by the lower clear signal (CLR) of the control unit 11, and the all@0'' which is input separately by the load signal CLOAD). Or set all '1' and up/down switching signal (
Add the LSD signal sent by ADC2 applied to its clock input according to the set value of all @ 0 @ or perform a trial calculation operation from all ° 1 # and compare the counting output with the second comparison. 0 sent to section 15b
In this embodiment, since the configuration is as described above, the control section 1
1 is the top 4 bits when testing the top 4 bits) 00
For example, 0010 is selectively added to 00 as the lower 4 bits in order to correct the entertainment difference, leakage, and profit.O<)00010
0 is applied to the DAC 12 to generate a corresponding analog voltage, and the switch section 14 is applied to output t-A of the DAC 12.
DC20 and the comparison timing signal is applied to the first
It is applied only to the comparator 15a and sends out the upper 4 bits as a reference signal for comparison and verification to execute the comparison operation with the upper 4 bits of the ADC 20. Therefore, an output is also generated on the lower 4 bits of the ADC 20, but in this case it is ignored.・
Next, gradually increase the upper 4 bits to 0000 Eri 111
Test in order from 1 to 1.

At this time as well, 0100 shall be added to the lower 4 bits in the same way. When testing the lower 4 bits, the bottom pressure control section 11 sends a clock to the test signal generation section 13 to change from Ov to 5 bits. A corresponding lamp voltage is generated, the switch section 14 is used to select the test signal generating section 131i, and the voltage t'' is applied to the ADc20. At the same time, the counter 16 is set to 0''1 (y).

As the up mode, the LSDtl-count of the ADC 20 is added and sent to the second comparison section 15b, and the comparison timing signal is sent only to the second comparison section 15b and the upper 4 bits are ignored.The 0ADC 20 responds according to the increase in lamp voltage. The lower 4-bit output is sent out, and the second comparator 15b compares it with the output of the counter. A direct comparison is 3 bits excluding the LSB out of 4 bits, but the LSB is verified by the operation of the counter 16. ◎At the timing of the drop in lamp voltage, all "t" are set to 1.
ADC20 by p/down signal and jdown module
Subtraction is performed every time the LSDt of the LSDt is received. As for the lower 4 bits, it is possible to continuously check the step changes in the digital signal due to the application of the lamp voltage that changes continuously from the O port, so it is possible to judge whether the operation is good or bad, although it is not possible to compare the lower 4 bits overall. @Of course, if the first comparing section 15a and the second comparing section 15b do not find a match, 1 is sent as an error signal via OR.

1) As described in detail, according to the present invention, ADCt--an expensive fl? It is useful because it provides a means to accurately test the operation of the ADC with easy operation without relying on the 'ffl reference power supply.

[Brief explanation of the drawing]

FIG. 1 shows parallel type A in the conventional and one embodiment of the present invention.
A block diagram of an A/D converter (ADC), FIG. 2 shows its conversion characteristics, FIG. 3 shows a block diagram of a test method for an A/D converter (ADC) in an embodiment of the present invention, and FIG. 1st. 0 showing a block diagram of the second comparison section, 10 is the test device, 20 is the input DC of the test object,
LL is a control unit, L2 is a digital-to-analog converter (D
AC), L3 is a test signal generation section, 14 is a switch section,
15a is the first comparison section, L5b is the second comparison section, and 16 is the counter.

Claims (1)

[Scope of Claims] In a test system in an intermediate or complete mounting unit configured by mounting and connecting an A/D converter element with other additional circuit elements, the test device is configured to comply with the specifications of the A/D converter on the mounting unit. a D/4 conversion means for generating a reference analog voltage by applying a reference digital signal corresponding to the upper m bits of the converter and including a corrected lower charger; n+1
A ramp voltage generating means for sending out a ramp voltage signal that continuously changes to a maximum tEE comparable to the bit, and a first comparing means for comparing the output in each of the upper m bits with a reference digital signal applied to the D/A converting means. Means for counting the minimum scale bit signal and each lower n
A second comparing means is provided for comparing the output in the bit with the output of the counting means, and the test l#i! The control part of the device is D/
The A converting means applies each analog reference voltage to the converter, ignoring the lower n bits of the converter, and the first comparing means compares and verifies the output of the upper m bits with the reference digital signal. A characterized in that the voltage generating means applies a lamp voltage, the upper m bits are ignored, and the second comparing means compares and verifies the output of the lower n bits with the output of the counting means to perform the test. /D converter test method.