JPS6333011A - Pll oscillator - Google Patents

Abstract

PURPOSE:To obtain an oscillating output with high accuracy by sample-holding the initial value of a phase difference signal outputted by a phase comparator in proportion to the phase difference between a reference oscillator output an a voltage controlled oscillator output immediately after oscillation is started, subtracting the initial value from a phase difference signal and keeping the control voltage of a voltage controlled oscillator to a constant value. CONSTITUTION:A pulse 108a to instruct an oscillating starting is shaped to a pulse 105a of the integer-fold pulse width of the period of a reference oscillating output 100 by a waveform shaping device 8. A voltage controlled oscillator 6 stops the oscillation with a pulse 105a. At this time, for a phase comparator 2, the average value of a phase difference signal 101a during the oscillating stopping period, which is the output, comes to be zero by using a multiplication type. A sample holding circuit 3 detects and holds the average value during a pulse 106b period of a phase difference signal 101b and inputs a holding voltage 102b to a subtracter circuit 4 and a holding voltage 102b is inputted to a subtracter circuit 4. The holding voltage 102b only for the phase difference signal 101b is subtracted by the subtracter circuit 4. Thus, a control voltage 107 of the voltage controlled oscillator 6 can be always kept to a constant value and an oscillating output 104 having a frequency accuracy determined by a reference oscillator 1 can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a PLL oscillator whose oscillation start timing can be controlled by an externally applied signal, and in particular,
The present invention relates to a PLL oscillator suitable for obtaining high oscillation frequency accuracy.

[Conventional technology]

Conventionally, a PLL oscillator whose oscillation start timing can be externally controlled is, for example, the 5359A manufactured by Huwlett Paracard.
Time Synthesizer, Temporary Operating and Service Manual (1978), pp. 8-45 to 8-46 (HEWLETT PA
CKARD 5359A TIME SYNTHE
SIZERlTEMPORARY 0PERATIN
G AND 5ERVICE MANUAL (1
978), p8-45 to p8-46),
The configuration is shown in FIG. A conventional example will be described below with reference to FIG. A conventional PLL oscillator whose oscillation start timing can be controlled externally has a reference oscillator 1 and an input pulse 20.
The voltage controlled oscillator 6 starts oscillation with 0, detects the frequency difference between the reference oscillation output 201 from the reference oscillator 1 and the oscillation output 202 from the voltage controlled oscillator 6, and generates a frequency signal 2.
03, a divider 11 that divides the oscillation output 202 by N, a phase comparator 2 that compares the phases of the frequency signal 203 and the divided output 204, and a phase difference signal 205 from the phase comparator 2. It consists of a digital sample and hold circuit 13 for detection and holding, and a switch 14.

The operation of the oscillator having the above configuration will first be described with the switch 14 switched to the a side. The frequency of the reference oscillation output 201 of the reference oscillator 1 is set to f2°1, and the voltage controlled oscillator 6
When the frequency of the oscillation output 202 of the mixer 10 is f2゜, the frequency of the frequency output 203 of the mixer 10 is f2゜, and the frequency of the divided output 204 of the frequency divider 11 is f2゜, the frequency division number is given by the following equation. The relationship holds true.

fzaa = fxox ftoz ・
・' ...(1) f2゜4=f2゜, /N
(2) Furthermore, the phase comparator 2 compares the phases of the frequency signal 203 from the mixer 10 and the frequency divided output 204 from the frequency divider 11, and sends the phase difference signal 205 to the switch 14. Since it is a PLL configuration in which the control voltage 207 of the voltage controlled oscillator 6 is fed back through
...(3), and the oscillation output 202 determined by the frequency accuracy of the reference oscillator 1 is obtained.

The voltage controlled oscillator 6 starts oscillating with a pulse 200 applied from the outside. At this time, the frequency divider 11 and the phase comparator 2 stop their operation by the output 208 from the control circuit 12, so the entire oscillator operates in an open loop, and the voltage controlled oscillator 6 operates at its free-running frequency. Continue oscillation. Thereafter, when the phases of the oscillation output 202 and the reference oscillation output 201 match, the control circuit 12 operates the splitter 11 and the phase comparator 2 based on the output of the mixer 10, and the oscillation output 202 is controlled by the PLL.

However, since the phase comparator 2 operates at a frequency of f2°,=f2°4=f2112/N, if the pulse 200 is applied at a frequency higher than this, the PLL operation becomes impossible. Therefore, at this time, the switch 14 is switched to the b side, and the digital sample and hold circuit 13 detects and holds the output voltage of the phase comparator 2, and applies the held voltage 206 as the control voltage 207 to the voltage controlled oscillator 6. PL
Performs open loop operation without L control.

As described above, conventionally, there always exists a time when open-loop operation occurs, and no consideration was given to the oscillation frequency accuracy during this period.

[Problem that the invention seeks to solve]

In the above conventional technology, there is always an open loop operation time from the start of oscillation until PLL control is performed, and the period of applying the pulse instructing the start of oscillation is longer than the operating period of the phase comparator in the PLL. If the size is small, PLL control cannot be performed and it is necessary to switch to open loop operation, resulting in a problem that highly accurate oscillation output cannot be obtained.

An object of the present invention is to eliminate the time for open loop operation, constantly perform PLL control, and obtain a highly accurate oscillation output.
The object of the present invention is to provide an L oscillator.

[Means for solving problems]

The above purpose is to sample and hold the initial value of a phase difference signal output by a phase comparator in proportion to the phase difference between the reference oscillator output and the voltage controlled oscillator output immediately after starting oscillation in an oscillator with a PLL configuration, This is achieved by subtracting its initial value from the phase difference signal to keep the control voltage of the voltage controlled oscillator at a constant value.

The present invention comprises a reference oscillator and a voltage controlled oscillator, a multiplier type phase comparator that compares the outputs of both, and a waveform shaper that shapes the pulse width for controlling oscillation to an integral multiple of the period of the reference oscillation output. This PLL oscillator is constructed by providing means for detecting and holding the output signal of the phase comparator immediately after the start of oscillation, and means for subtracting the held signal from the output signal of the phase comparator.

[Effect]

With the above configuration, the waveform shaper shapes the pulse width of the signal that controls the start of oscillation to an integral multiple of the period of the reference oscillator output, and the voltage controlled oscillator stops oscillation by the output pulse of the waveform shaper, and Oscillation starts from the falling edge of the pulse. By using a multiplication type phase comparator,
The DC component of the phase comparator output during the oscillation stop period becomes 0, and does not affect the control of the PLL. The sample and hold circuit detects and holds the output voltage of the phase comparator immediately after the voltage controlled oscillator starts oscillating. A subtraction circuit subtracts the output voltage of the sample and hold circuit from the output voltage of the phase comparator. Through the above operation, the PLL is controlled while the control voltage of the voltage controlled oscillator is kept at a steady value, so that an oscillation output that maintains the phase at the start of oscillation can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

Figure 1 shows a PLL that can control the oscillation start timing according to the present invention.
This shows the configuration of an embodiment of the oscillator, and FIG. 2 shows the operating waveforms of the embodiment. As shown in FIG. 1, the PLL oscillator of this embodiment whose oscillation start timing can be controlled is a reference oscillator 1, a voltage controlled oscillator 61 whose oscillation/stop can be instructed by a pulse 105, and a comparison between an oscillation output 104 and a reference oscillation output 100. The multiplier type phase comparator 2 detects the phase difference signal 101 using the sample pulse 106.
Sample/hold circuit 3 to hold, phase difference signal 101
It consists of a subtraction circuit 4 that subtracts the holding voltage 102 from the oscillation output, a low-pass filter 5, a delay circuit 7 that delays the pulse 105, and a waveform shaper 8 that shapes the pulse width to an integral multiple of the period of the reference oscillation output.

Next, the operation of the oscillator having the above configuration will be explained using FIG. 1 and FIG. 2. The pulse 108a instructing the start of oscillation is
The waveform shaper 8 shapes the pulse 105a into a pulse 105a having a pulse width that is an integral multiple of the period of the reference oscillation output 100. The voltage controlled oscillator 6 stops oscillating with the pulse 105a.

At this time, by using a multiplication type, the phase comparator 2 outputs a phase difference signal 101a during the oscillation stop period.
The average value of is O.

The voltage controlled oscillator 6 starts oscillating from the falling edge of the pulse 105a, and the oscillation output 104b is input to the phase comparator 2. The phase comparator 2 compares the phases of the oscillation output 104b and the reference oscillation output 100, and outputs a phase difference signal 101b. The sample and hold circuit 3 receives the pulse 105a
The sample pulse 106 obtained by applying to the delay circuit 7
b detects and holds the average value of the phase difference signal 101b during the pulse 106b period, and inputs the holding voltage 102b to the subtraction circuit 4. The phase difference signal 101b is subtracted by the holding voltage 102b by the subtraction circuit 4, and the subtraction output 1
03b is applied as a control voltage 107 to the voltage controlled oscillator 6 via the low-pass filter 5. In this way, PLL control is performed so that the phases of the oscillation output 104b and the reference oscillation output 100 match.

Next, a case will be described in which the pulse 108c is continuously applied in the above state. As above, pulse 108c
becomes a pulse 105c via the waveform shaper 8, and the voltage controlled oscillator 6 stops oscillating. During the oscillation stop period, the average value of the output 101c of the phase comparator 2 is 0, and since the sample-and-hold circuit 3 is reset by the pulse 105c, the average value of the output 103c of the subtraction circuit 4 is also 0. Next, when the pulse 105c falls, the voltage controlled oscillator 6 starts oscillating, and the phase comparator 2 compares the phases of the oscillation output 104d and the reference oscillation output 100, and outputs a phase difference signal 101d. Thereafter, in the same way as when the pulse 105a was input, the sample-and-hold circuit 3
The average value of the phase difference signal 101d is detected and held by the sample pulse 106d obtained by applying the pulse 105c to the delay circuit 7, and the holding voltage 102d is applied to the subtraction circuit 4.
Enter. The phase difference signal 101d is subtracted by the holding voltage 102d by the subtraction circuit 4 to obtain a subtraction output 103d. The subtraction output 103d is passed through the low-pass filter 5,
Applied as a control voltage 107d of the voltage controlled oscillator 6,
PLL control is performed so that the phases of the oscillation output 104d and the reference oscillation output 100 match.

As explained above, according to the present embodiment, the initial value of the phase difference signal 101, which changes depending on the timing at which the voltage controlled oscillator 6 starts oscillation, is subtracted by the sample-and-hold circuit 3 and the subtraction circuit 4. As a result, the control voltage 107 of the voltage controlled oscillator 6 can always be kept at a constant value, so that the oscillation output 104 with the frequency accuracy determined by the reference oscillator 1 can be obtained while maintaining the phase at the start of oscillation.

〔Effect of the invention〕

According to the present invention, immediately after applying an oscillation start pulse, the initial value of the phase difference signal output by the phase comparator in proportion to the phase difference between the reference oscillator output and the voltage controlled oscillator output is detected and held,
By subtracting this value from the phase difference signal, the control voltage of the voltage controlled oscillator is maintained at a constant value, and PLL control is applied to other disturbances, so the oscillation output has frequency accuracy determined by the reference oscillator. can be obtained.

[Brief explanation of drawings]

Figure 1 shows a PLL that can control the oscillation start timing according to the present invention.
A block diagram showing the configuration of one embodiment of the oscillator, FIG. 2 is a waveform diagram showing the operating waveforms of the embodiment in FIG. 1, and FIG. 3 is a block diagram showing a conventional example of a PLL oscillator that can control the oscillation start timing. It is. Explanation of symbols 1... Reference oscillator, 2... Phase comparator. 3...Sample/hold circuit. 4... Subtraction circuit, 5... Low pass filter, 6...
... Voltage controlled oscillator, 7... Delay circuit, 8... Waveform shaper, 10... Mixer, 11... Frequency divider, 12... Control circuit, 13... Digital sample -Hold circuit, 14...switch. Representative Patent Attorney Junnosuke Nakamura (2)

Claims (1)

[Claims] 1. Consists of a reference oscillator and a voltage controlled oscillator, a multiplication type phase comparator that compares the outputs of both, and a waveform shaper that shapes the pulse width for controlling oscillation to an integral multiple of the period of the reference oscillator output. The PLL oscillator is characterized by being provided with means for detecting and holding the output signal of the phase comparator immediately after the start of oscillation, and means for subtracting the held signal from the output signal of the phase comparator. PLL oscillator.