JPH06232740A - Weak coupling oscillator utilizing multi-stage moving average processing - Google Patents

Weak coupling oscillator utilizing multi-stage moving average processing

Info

Publication number
JPH06232740A
JPH06232740A JP5037500A JP3750093A JPH06232740A JP H06232740 A JPH06232740 A JP H06232740A JP 5037500 A JP5037500 A JP 5037500A JP 3750093 A JP3750093 A JP 3750093A JP H06232740 A JPH06232740 A JP H06232740A
Authority
JP
Japan
Prior art keywords
circuit
signal
averaging circuit
averaging
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5037500A
Other languages
Japanese (ja)
Inventor
Hitoshi Ujiie
仁 氏家
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Communication Equipment Co Ltd
Original Assignee
Toyo Communication Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Communication Equipment Co Ltd filed Critical Toyo Communication Equipment Co Ltd
Priority to JP5037500A priority Critical patent/JPH06232740A/en
Publication of JPH06232740A publication Critical patent/JPH06232740A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To remarkably reduce a time required for an output signal synchronously with a reference signal by executing average processing while switching dynamically a time constant from a small value to a large value sequentially in response to the lock state of the synchronization system. CONSTITUTION:A phase difference between a signal fin and an output signal fout of a reference oscillator 11 is detected by a DPC 12 and the phase difference is fed to a 1st averaging circuit 13-1 having a comparatively shorter (smaller) time constant, in which rough phase data are detected by simple average processing. A switch circuit 14 is set to select at first an output of the circuit 13-1 and the selected signal is fed to a proportion integration circuit 16. The oscillated frequency of a VCO 18 is highly stable synchronously with a signal from the reference oscillator by the action of a PLL. A threshold level used to make comparison with phase data corresponding to each averaging circuit is stored in the switch control circuit 15, and when the threshold level outputted from the selected averaging circuit at that time exceeds the threshold level or less than the threshold level, that is, the switch circuit 14 is controlled while the PLL of each averaging circuit is locked-in to select the average circuit on purpose.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は弱結合発振器に関し、詳
しくは入力信号の周波数に出力信号周波数を高精度に同
期させ、入力信号が途絶してもそれ以前の周波数情報に
基づいて正確な発振周波数を維持でき、しかも入力信号
に混入する位相変動を除去し位相及び周波数が極めて安
定な発振器に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a weakly coupled oscillator, and more specifically, it synchronizes an output signal frequency with the frequency of an input signal with high accuracy so that even if the input signal is interrupted, accurate oscillation is performed based on frequency information before that. The present invention relates to an oscillator capable of maintaining a frequency and removing a phase fluctuation mixed in an input signal and having an extremely stable phase and frequency.

【0002】[0002]

【従来技術】基準となる信号に弱結合し、た弱結合発振
器としては図1に示すものが知られている。このブロッ
クは基準発振器1の信号finと出力信号fout の位相を
比較するDPC(デジタル位相比較器)2と、上記DP
Cによって検出された位相データの短期的な変動を単純
平均処理によって除去する平均回路(AVERAGER
回路)3と、平均された信号を比例積分しデジタル信号
に変換するための比例積分回路4と、比例積分されたデ
ジタル信号を直流信号に変換するD/Aコンバ−タ5
と、この直流電圧信号によって発振周波数が制御される
VCO(電圧制御発振器)6とからなっており、上記V
CO6の出力がfout となると共に、その一部は上記D
PC2にフィ−ドバックされるようになっている。
2. Description of the Related Art As a weakly coupled oscillator weakly coupled to a reference signal, one shown in FIG. 1 is known. This block includes a DPC (Digital Phase Comparator) 2 for comparing the phase of the signal f in of the reference oscillator 1 with the phase of the output signal f out , and the above DP.
An averaging circuit (AVERAGER) that removes short-term fluctuations in the phase data detected by C by simple averaging processing.
Circuit) 3, a proportional integration circuit 4 for proportionally integrating the averaged signal to convert it into a digital signal, and a D / A converter 5 for converting the proportionally integrated digital signal into a DC signal.
And a VCO (voltage controlled oscillator) 6 whose oscillation frequency is controlled by this DC voltage signal.
The output of CO6 becomes f out, and part of it becomes D
It is designed to be fed back to the PC2.

【0003】また上記基準発振器1は例えば恒温槽方式
の長期的且つ短期的に高安定度の発振器が使用され、上
記平均回路によって入力信号の単周期の位相変動が除去
され、基準発振器の真の周波数情報に基づいて導出され
た直流電圧によって上記VCOが制御され、極めて安定
な周波数信号が発生されるようになっている。
The reference oscillator 1 is, for example, a thermostat type oscillator having a high stability in the long term and the short term. The averaging circuit removes a single cycle phase fluctuation of the input signal, and the reference oscillator is a true oscillator. The VCO is controlled by the DC voltage derived based on the frequency information, and an extremely stable frequency signal is generated.

【0004】上記のような従来の弱結合発振器において
は、入力する基準信号の位相変動が大きいときは平均回
路3の時定数を大きく設定すべきで、また逆に位相変動
が小さい場合は時定数を小さく設定すべきであるが、従
来の回路においてはこの時定数は固定であって、入力信
号の位相変動に対応するようには構成されていなかった
ため、一般には時定数を大きく設定することによって、
大きな位相変動をも除去し得る様になっていた。
In the conventional weakly coupled oscillator as described above, the time constant of the averaging circuit 3 should be set large when the phase fluctuation of the input reference signal is large, and conversely when the phase fluctuation is small. Should be set small, but in the conventional circuit, this time constant was fixed and was not configured to correspond to the phase fluctuation of the input signal. ,
It was possible to remove even large phase fluctuations.

【0005】しかしながら、このように時定数を大きく
設定すると、平均回路3から出力される信号の周期が長
期化し、従ってVCO6が基準信号に同期するまでに長
時間を要することになり、弱結合発振器としての使用範
囲が限定されてしまうと云う欠点があった。即ち、電源
投入から比較的短時間に信号を得たい場合は使用不可能
であった。
However, if the time constant is set to a large value in this way, the period of the signal output from the averaging circuit 3 becomes long, so that it takes a long time for the VCO 6 to synchronize with the reference signal, and the weakly coupled oscillator is used. However, there was a drawback that the range of use was limited. That is, it was impossible to use when a signal was to be obtained in a relatively short time after the power was turned on.

【0006】[0006]

【発明の目的】本発明は上述したような従来の弱結合発
振器の欠点を排除するためのもので、基準信号の大小の
位相変動の全てに対応することができると共に、出力信
号が基準信号に同期するまでの時間を大幅に短縮するこ
とができる弱結合発振器を提供することを目的としてい
る。
It is an object of the present invention to eliminate the drawbacks of the conventional weakly coupled oscillator as described above, and it is possible to deal with all the large and small phase fluctuations of the reference signal, and at the same time, make the output signal the reference signal. It is an object of the present invention to provide a weakly coupled oscillator that can significantly reduce the time required for synchronization.

【0007】[0007]

【発明の概要】上記目的を達成するため本発明では、基
準信号と出力信号の位相を比較する位相比較器と、所定
の時定数を持った平均回路と、この平均回路出力を直流
電圧に変換する回路と、該直流電圧によって制御する電
圧制御発振器と、この電圧制御発振器出力を外部に出力
すると共にその一部を前記位相比較器にフィ−ドバック
する手段とをもった弱結合発振器において、前記平均回
路が互いに時定数が異なる複数の平均回路を備えたもの
であり、出力と前記基準発振器信号との位相差の大小に
応じて、前記平均回路を切替える切替手段を備えたこと
を特徴とする。
SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a phase comparator for comparing the phases of a reference signal and an output signal, an averaging circuit having a predetermined time constant, and the averaging circuit output converted to a DC voltage. A weakly coupled oscillator having a circuit, a voltage controlled oscillator controlled by the DC voltage, and means for feeding back the voltage controlled oscillator output to the outside and feeding back a part of the voltage controlled oscillator to the phase comparator. The averaging circuit is provided with a plurality of averaging circuits having different time constants, and the averaging circuit is provided with a switching means for switching the averaging circuit according to the magnitude of the phase difference between the output and the reference oscillator signal. .

【0008】[0008]

【実施例】以下、図示した実施例に基づいて本発明の弱
結合発振器について詳細に説明する。図1は本発明の一
実施例を示すブロック構成図であり、ここに示す装置
は、基準発振器1からの信号と出力する信号との位相差
を検出するDPC(デジタル位相比較器)2と、第1の
平均回路3−1と、第2から第5までの平均回路3−2
〜3−5を並列に接続したブロックと、上記第1から第
5までの平均回路の一つを選択するスイッチ回路14
と、第の平均回路の出力と第2から第5の平均回路の出
力を供給すると共にこれらの信号に基づいて前記スイッ
チ回路14を制御するスイッチ制御回路15と、上記ス
イッチ回路出力を比例積分する比例積分回路16と、積
分回路からのデジタル出力をアナログ信号に変換するD
/Aコンバ−タ17と、アナログ化された直流信号によ
って周波数を制御する電圧制御発振器(VCO)18と
からなっており、上記VCO18の出力の一部が上記位
相比較器12にフィ−ドバックされるように構成された
ものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The weakly coupled oscillator of the present invention will be described in detail below with reference to the illustrated embodiments. FIG. 1 is a block diagram showing an embodiment of the present invention. The apparatus shown here is a DPC (digital phase comparator) 2 for detecting a phase difference between a signal output from a reference oscillator 1 and an output signal. The first averaging circuit 3-1 and the second to fifth averaging circuits 3-2
Block 3 to 5 connected in parallel, and a switch circuit 14 for selecting one of the first to fifth averaging circuits
And a switch control circuit 15 which supplies the output of the first averaging circuit and the outputs of the second to fifth averaging circuits and controls the switch circuit 14 based on these signals, and proportionally integrates the output of the switch circuit. Proportional integrator circuit 16 and D that converts the digital output from the integrator circuit into an analog signal
A / A converter 17 and a voltage controlled oscillator (VCO) 18 which controls the frequency by an analog DC signal. A part of the output of the VCO 18 is fed back to the phase comparator 12. It is configured to.

【0009】なお、上記5個の平均回路13−1〜13
−5は夫々異なる時定数を持ち、第一の平均回路が最も
小さい時定数をもち、第五の平均回路13−5が最も大
きな時定数を持ち、その間の平均回路は順次段階的に異
なった時定数が設定されている。
The above five average circuits 13-1 to 13-13
-5 has different time constants, the first averaging circuit has the smallest time constant, the fifth averaging circuit 13-5 has the largest time constant, and the averaging circuits in the meantime differ stepwise. The time constant is set.

【0010】この構成において動作を説明すると、入力
された基準発振器11の信号finと出力信号fout との
位相差がDPC12によって検出され、次の第一の平均
回路13−1に供給される。第一の平均回路は上記のよ
うに比較的短い(小さい)時定数を持ったもので、単純
平均を行うことによっておよその位相データを検出す
る。
To explain the operation in this configuration, the phase difference between the input signal f in of the reference oscillator 11 and the output signal f out is detected by the DPC 12 and supplied to the next first averaging circuit 13-1. . The first averaging circuit has a relatively short (small) time constant as described above, and detects approximate phase data by performing simple averaging.

【0011】上記スイッチ回路14は最初は第一の平均
回路13−1の出力を選択する様に設定され、比例積分
回路16に供給する。比例積分回路16、D/Aコンバ
−タ17及びVCOの動作と作用は従来技術と変わりが
ないので説明を省略するが、VCO18の発振周波数は
フェ−ズロックル−プの作用によって基準発振器の信号
に同期して高安定度となる。
The switch circuit 14 is initially set to select the output of the first averaging circuit 13-1, and supplies it to the proportional-plus-integration circuit 16. The operations and functions of the proportional-plus-integrator circuit 16, the D / A converter 17 and the VCO are the same as those of the prior art, so that the description thereof will be omitted. However, the oscillation frequency of the VCO 18 becomes the signal of the reference oscillator due to the operation of the phase lock loop. High stability is achieved in synchronization.

【0012】ただし、以上の動作では第一の平均回路の
時定数が小さいため、同期するまでの時間は短くなる
が、大きな位相変動には追従できず周波数の精度は劣っ
たものとなるので、次に説明する様に順次平均回路を切
り替える操作を行う。
However, in the above operation, since the time constant of the first averaging circuit is small, the time until the synchronization becomes short, but a large phase fluctuation cannot be followed and the frequency accuracy becomes inferior. As described below, the averaging circuit is sequentially switched.

【0013】上記スイッチ制御回路15には各平均回路
に対応した位相データと比較するスレシホ−ルド値が記
憶されており、その時選択した平均回路から出力される
位相データがスレシホ−ルドを越えた時、又はスレシホ
−ルド値以下になった時、即ち、夫々の平均回路におい
てフェ−ズロックル−プがロックインした状態で上記ス
イッチ回路14を制御して選択する平均回路を切り替え
る。
The switch control circuit 15 stores the threshold value to be compared with the phase data corresponding to each averaging circuit, and when the phase data output from the selected averaging circuit exceeds the threshold value at that time. , Or below the threshold value, that is, in the state where the phase lock loop is locked in in each averaging circuit, the switching circuit 14 is controlled to switch the averaging circuit to be selected.

【0014】上記平均回路の切替方法は、基本的には順
番に時定数が小さい方から大きい方へ移行することによ
って、より高精度の出力信号を得るが、一旦最大時定数
にて同期が取れた状態において、観測される位相変動が
小さい時に、これに適した平均回路に切り替えるように
制御することも考えられる。
In the above averaging circuit switching method, basically, a higher-precision output signal is obtained by sequentially shifting from a smaller time constant to a larger time constant, but synchronization is once achieved with the maximum time constant. In such a state, when the observed phase fluctuation is small, it may be possible to control so as to switch to an averaging circuit suitable for this.

【0015】このように平均回路の時定数を順次切り替
えるようにすれば電源投入から同期がとれるまでの時間
を大幅に短縮することができる。更に、順次時定数が大
きな平均回路に切り替えた際であっても、前段の平均回
路によって既に小時定数による平均処理が済んでいるこ
とから、次の大きな時定数処理による同期に要する時間
が短縮される効果もある。また、後段の平均処理に移動
平均処理を採用したので後段の平均回路からデータが出
力される周期と、前段の平均回路からデータが出力され
る周期が同一となることから、後段に大きな時定数の平
均回路を選択した場合であってもVCOが無制御状態に
なることがなく、安定した出力信号を得ることができ
る。
By sequentially switching the time constants of the averaging circuit in this way, the time from power-on to synchronization can be greatly shortened. Furthermore, even when switching to an averaging circuit with a large time constant in sequence, the averaging circuit in the previous stage has already completed the averaging processing with a small time constant, so the time required for synchronization with the next large time constant processing is shortened. There is also an effect. In addition, since moving average processing is adopted for the averaging processing in the subsequent stage, the cycle in which data is output from the averaging circuit in the subsequent step and the cycle in which data is output from the averaging circuit in the previous step are the same, so a large time constant is applied to the subsequent step. Even if the averaging circuit is selected, the VCO does not enter the uncontrolled state and a stable output signal can be obtained.

【0016】また、時定数が大きな平均処理を行う場
合、サンプル数が多くなるからその計算処理に長時間を
要することになるが、本発明においては時定数が小さい
平均回路において得た結果を用いて次段の平均処理を行
うので、後段の処理に要する時間が短縮でき、各平均回
路における計算処理負担を大幅に軽減することにもな
る。
Further, when the averaging process having a large time constant is performed, the number of samples increases, and therefore the calculation process takes a long time. In the present invention, the result obtained by the averaging circuit having a small time constant is used. Since the next-stage averaging process is performed, the time required for the subsequent-stage process can be shortened, and the calculation processing load on each averaging circuit can be significantly reduced.

【0017】[0017]

【発明の効果】本発明は以上説明したように、時定数が
小さなものから大きなものへと、同期系の引き込み状態
に応じて、順次ダイナミックに切替ながら平均処理を行
うように構成したので、従来の弱結合発振器に比べて、
同期に要する時間を大幅に短縮することができ、電源投
入から比較的短時間で使用可能になる。
As described above, according to the present invention, the averaging process is performed while dynamically switching from a small time constant to a large time constant in accordance with the pulling state of the synchronous system. Compared to the weakly coupled oscillator of
The time required for synchronization can be greatly reduced, and the device can be used in a relatively short time after the power is turned on.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すブロック構成図であ
る。
FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】従来の弱結合発振器のブロック構成図である。FIG. 2 is a block diagram of a conventional weakly coupled oscillator.

【符号の説明】[Explanation of symbols]

1、11 基準発振器、 2、12 デジタル位相比
較器、3、13−1、13−2、13−3、13−4、
13−5 平均回路、4、16 比例積分回路、
5、17 デジタルアナログ変換器、6、18 電圧制
御発振器、 14 切替スイッチ、 15 スイッチ制
御回路。
1, 11 Reference oscillator, 2, 12 Digital phase comparator, 3, 13-1, 13-2, 13-3, 13-4,
13-5 Averaging circuit, 4, 16 Proportional integrating circuit,
5, 17 digital-analog converter, 6, 18 voltage controlled oscillator, 14 changeover switch, 15 switch control circuit.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基準信号と出力信号の位相を比較する位
相比較器と、所定の時定数を持った平均回路と、この平
均回路出力を直流電圧に変換する回路と、該直流電圧に
よって制御する電圧制御発振器と、この電圧制御発振器
出力を外部に出力すると共にその一部を前記位相比較器
にフィ−ドバックする手段とをもった弱結合発振器にお
いて、前記平均回路が互いに時定数が異なる複数の平均
回路を備えたものであり、出力と前記基準発振器信号と
の位相差の大小に応じて、前記平均回路を切替える切替
手段を備えたことを特徴とする多段階移動平均処理によ
る弱結合発振器。
1. A phase comparator for comparing the phases of a reference signal and an output signal, an averaging circuit having a predetermined time constant, a circuit for converting the output of the averaging circuit into a DC voltage, and control by the DC voltage. In a weakly-coupled oscillator having a voltage-controlled oscillator and means for outputting the output of the voltage-controlled oscillator to the outside and feeding back a part of the voltage-controlled oscillator to the phase comparator, the averaging circuit has a plurality of time constants different from each other. A weakly coupled oscillator according to a multi-step moving average process, comprising: an averaging circuit, comprising switching means for switching the averaging circuit according to a magnitude of a phase difference between an output and the reference oscillator signal.
JP5037500A 1993-02-02 1993-02-02 Weak coupling oscillator utilizing multi-stage moving average processing Pending JPH06232740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5037500A JPH06232740A (en) 1993-02-02 1993-02-02 Weak coupling oscillator utilizing multi-stage moving average processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5037500A JPH06232740A (en) 1993-02-02 1993-02-02 Weak coupling oscillator utilizing multi-stage moving average processing

Publications (1)

Publication Number Publication Date
JPH06232740A true JPH06232740A (en) 1994-08-19

Family

ID=12499252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5037500A Pending JPH06232740A (en) 1993-02-02 1993-02-02 Weak coupling oscillator utilizing multi-stage moving average processing

Country Status (1)

Country Link
JP (1) JPH06232740A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400318B1 (en) * 2001-06-25 2003-10-01 주식회사 하이닉스반도체 Clock synchronization device
JP2009157679A (en) * 2007-12-27 2009-07-16 Yaskawa Electric Corp Serial data movement averaging device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400318B1 (en) * 2001-06-25 2003-10-01 주식회사 하이닉스반도체 Clock synchronization device
JP2009157679A (en) * 2007-12-27 2009-07-16 Yaskawa Electric Corp Serial data movement averaging device

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