JPS59190725A - Phase synchronizing circuit - Google Patents
Phase synchronizing circuitInfo
- Publication number
- JPS59190725A JPS59190725A JP58064753A JP6475383A JPS59190725A JP S59190725 A JPS59190725 A JP S59190725A JP 58064753 A JP58064753 A JP 58064753A JP 6475383 A JP6475383 A JP 6475383A JP S59190725 A JPS59190725 A JP S59190725A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- output
- input signal
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、入力信号の周波数に追従して電圧制御発振器
の発振周波数を変化させる位相同期回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase locked circuit that changes the oscillation frequency of a voltage controlled oscillator in accordance with the frequency of an input signal.
従来、位相同期回路の引込時間を早める方法として同期
状態の位相比較器の出力電圧を一定時間、例えは入力信
号が断になったときから再び入力信号が入力信号が入力
されるまで入力信号が断になる以前の電圧を保持し非同
期状態の間、電圧制御発振器の発振周波数や位相がずれ
ないようにする方法がある。Conventionally, as a method to speed up the pull-in time of a phase-locked circuit, the output voltage of a phase comparator in a synchronized state is controlled for a certain period of time, for example, from when the input signal is cut off until the input signal is input again. There is a method to maintain the voltage before the power failure and to prevent the oscillation frequency and phase of the voltage controlled oscillator from shifting during the asynchronous state.
しかしながらこの方法では入力信号が長時間にわたって
断になる場合には保持回路の保持時定数の制限があシ、
時間が経過するにつれて除々に保持電圧が大きくずれ、
電圧制御発振器の発振周波数が大きくずれるという欠点
があった。However, with this method, if the input signal is disconnected for a long time, there is a limit to the holding time constant of the holding circuit.
As time passes, the holding voltage gradually deviates greatly,
There was a drawback that the oscillation frequency of the voltage controlled oscillator shifted significantly.
本発明の目的は、前記欠点を解決した位相同期回路を提
供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked circuit which solves the above-mentioned drawbacks.
本発明の位相同期回路は、入力信号からに期信号を分離
して前記入力信号の可熱を検出する同期検出回路と、制
御信号に応答し発振周波数が変化する電圧制御発揚器と
、前記同期検出回路から出力される同期信号を微分する
微分回路と、前記電圧制御発振器の出力またはその分周
出力を積分する積分回路と、前記微分回路の出力信号に
よシ前記積分回路の出力を標本する標本回路と、前記同
期検出回路から出力される信号未検出信号によυ一定レ
ベル信号を出力する切替回路と、前記第１の標本回路と
前記切替回路の出力端子を接続して出力端子の信号レベ
ルを保持して前記制御信号とする保持回路とを備え、前
記入力信号に前記電圧制御発振器の発振出力を位相同期
させるようにしたことを特徴とする。The phase synchronization circuit of the present invention includes: a synchronization detection circuit that separates a phase signal from an input signal to detect heatability of the input signal; a voltage controlled oscillator whose oscillation frequency changes in response to a control signal; a differentiating circuit that differentiates the synchronization signal output from the detection circuit; an integrating circuit that integrates the output of the voltage controlled oscillator or its frequency-divided output; and sampling the output of the integrating circuit based on the output signal of the differentiating circuit. A sampling circuit, a switching circuit that outputs a constant level signal based on the signal not detected outputted from the synchronization detection circuit, and a signal at the output terminal by connecting the output terminals of the first sampling circuit and the switching circuit. The present invention is characterized in that it includes a holding circuit that holds a level and uses it as the control signal, and the oscillation output of the voltage controlled oscillator is phase-synchronized with the input signal.
以下、実施例について詳細に説明する。−第１図は本発
明の実施例であって、１は信号入力端子、２は入力信号
から同期信号を分離して入力信号の有無を検出する同期
検出回路、３は微分回路、４は微分回路の出力によシ積
分回路の出力を標本する標本回路、５は保持回路、６は
ループ・フィルタ、７は電圧制御発振器、８は分局器、
９は積分回路、１０は同期検出回路の出力信号によシ一
定レベル信号ＣＬＶを出力する切替回路である。１０入
力端子から入った信号は同期検出回路２で同期信号を分
離し微分回路３に供給されるとともに同期検出回路２で
入力信号の有無を検出し、入力信号が無い場合に電圧制
御発振器７がセンター周波数を出力する一定しベル信号
ＣＬＶを第２の標本回路１０で標本する制御をする。微
分回路３に供給さｎた同期信号は微分回路で標本化パル
スが生成されて、積分回路９から出力さｎる信号を標本
回路４で標本する。標本回路４と切替回路１０の出力は
接続されて保持回路５で電圧を保持するとともにループ
拳フィルタ６に供給さｎ高周波成分全とシ除いて電圧制
御発振器７に加えられる。電圧制御発振器７の出力信号
は分周器８によシ入力信号の同期信号と同じ周波数にな
るように分周さｎて積分回路９に出力される。積分回路
９の出力信号は標本側ｉ４０入力端子に供給さｒる。Examples will be described in detail below. - Figure 1 shows an embodiment of the present invention, in which 1 is a signal input terminal, 2 is a synchronization detection circuit that separates a synchronization signal from an input signal and detects the presence or absence of an input signal, 3 is a differentiation circuit, and 4 is a differentiation circuit. 5 is a holding circuit, 6 is a loop filter, 7 is a voltage controlled oscillator, 8 is a divider,
9 is an integrating circuit, and 10 is a switching circuit that outputs a constant level signal CLV based on the output signal of the synchronization detection circuit. The synchronization detection circuit 2 separates the synchronization signal from the input terminal 10 and supplies it to the differentiation circuit 3.The synchronization detection circuit 2 detects the presence or absence of an input signal, and if there is no input signal, the voltage controlled oscillator 7 A second sampling circuit 10 controls sampling of a constant bell signal CLV that outputs a center frequency. The synchronizing signal supplied to the differentiating circuit 3 is used to generate a sampling pulse, and the signal output from the integrating circuit 9 is sampled by the sampling circuit 4. The outputs of the sample circuit 4 and the switching circuit 10 are connected to each other, and the voltage is held in a holding circuit 5, and is supplied to a loop filter 6, where all high frequency components are removed and applied to a voltage controlled oscillator 7. The output signal of the voltage controlled oscillator 7 is divided by a frequency divider 8 to have the same frequency as the synchronizing signal of the input signal, and is output to an integrating circuit 9. The output signal of the integrating circuit 9 is supplied to the sample side i40 input terminal.
次にこの回路の動作例について第２図の各部波形図を用
いて説明する。ａは入力信号であシ、図の最小値レベル
が水平同期区間であシ、途中から入力信号が断になった
場合である。ｂは同期検出回路２から出力される同期信
号であシ、Ｃは微分回路３の出力信号であり、積分回路
９からの台形波状積分出力ｅを標本する。一方ｆは同期
検出回路２から出力される入力信号の有無を示す信号未
検出信号でアシ、入力信号が無い時に高レベルとなシ切
替回路１０にて一定しベルＣＬＶを出力する。ｇはルー
プ・フィルタに入力される標本化保持電圧を示し、ｄは
電圧制御発振器７の出力を入力信号の水平同期信号の周
波数と一致するように分周された出力である。入力信号
が断となシ標本信号Ｃが出力されなくなると標本化回路
４の出力は開放となると共に、同期信号の有無を示す信
号未検出信号ｆが高レベルとなシ切替回路１０が動作し
て標本化保持信号ｇは安定になる。従来のように切替回
路１０が無い場合は保持回路の時定数の制限からｇの破
線のように時間とともに上昇する０
以上説明したように、本発明によｎば、入力信号が長時
間にわたって断になっても電圧制御発振器の発振周波数
の変動が少なく、入力信号が再び入力されると短時間に
同期引込みが可能となる。Next, an example of the operation of this circuit will be explained using the waveform diagram of each part shown in FIG. A is the input signal, the minimum level in the figure is in the horizontal synchronization section, and the input signal is cut off midway through. b is a synchronization signal output from the synchronization detection circuit 2, C is an output signal of the differentiating circuit 3, and samples the trapezoidal waveform integral output e from the integrating circuit 9. On the other hand, f is an undetected signal outputted from the synchronization detection circuit 2 indicating the presence or absence of an input signal, which is at a high level when there is no input signal, and is kept constant in the switching circuit 10 to output a bell CLV. g indicates a sampled holding voltage input to the loop filter, and d is an output obtained by dividing the output of the voltage controlled oscillator 7 to match the frequency of the horizontal synchronizing signal of the input signal. When the input signal is interrupted and the sampling signal C is no longer output, the output of the sampling circuit 4 becomes open, and when the signal undetected signal f indicating the presence or absence of the synchronization signal becomes high level, the switching circuit 10 operates. The sampled hold signal g becomes stable. If there is no switching circuit 10 as in the conventional case, g will increase with time as shown by the broken line due to the limitation of the time constant of the holding circuit. Even if the oscillation frequency of the voltage controlled oscillator becomes smaller, the fluctuation in the oscillation frequency of the voltage controlled oscillator is small, and synchronization can be achieved in a short time when the input signal is input again.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図の動作を示す波形図である。
１・・・・・・入力端子、２・・・・・・同期検出回路
、３・・・・・・微分回路、４・・・・・・標本回路、
５・・・・・・保持回路、６・・・・・・ループ争フィ
ルタ、７・・・・・・電圧制御発振器、８・・・・・・
分周器、９・・・・・・積分回路、ＣＬＶ・・・・・・
一定レベル信号、１０・・・・・・切替回路、ａ・・・
・・・入力信号、ｂ・・・・・・同期信号、Ｃ・・・・
・・微分出力、ｄ・・・・・・分周出力、ｅ・・・・・
・積分出力、ｆ・・・・・・信号未検出信号、ｇ・・・
・・・標本保持信号。FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operation of FIG. 1. 1... Input terminal, 2... Synchronization detection circuit, 3... Differential circuit, 4... Sample circuit,
5... Holding circuit, 6... Loop competition filter, 7... Voltage controlled oscillator, 8...
Frequency divider, 9...Integrator circuit, CLV...
Constant level signal, 10...Switching circuit, a...
...Input signal, b...Synchronization signal, C...
...Differential output, d...Divide output, e...
・Integrated output, f...signal undetected signal, g...
...Sample holding signal.
Claims (1)
検出する同期検出回路と、制御信号に応答し発振周波数
が変化する電圧制御発振器と、前記同期検出回路から出
力される同期信号を微分する微分回路と、前記電圧制御
発振器の出力またはその分周出力を積分する積分回路と
、前記微分回路の出力信号によシ前記積分回路の出力を
標本する標本回路と、前記同期検出回路から出力される
信号未検出信号によシ一定レベル信号を出力する切替回
路と、前記標本回路と前記切替回路の出力端子を接続し
て出力端子の信号レベルを保持して前記制御信号とする
保持回路とを備え、前記入力信号に前記電圧制御発振器
の発振出力を位相同期させるようにしたことを特徴とす
る位相同期回路。a synchronization detection circuit that separates a synchronization signal from an input signal and detects the presence or absence of the input signal; a voltage-controlled oscillator whose oscillation frequency changes in response to a control signal; and a synchronization detection circuit that differentiates the synchronization signal output from the synchronization detection circuit. a differentiator circuit, an integrator circuit that integrates the output of the voltage controlled oscillator or its frequency-divided output, a sampling circuit that samples the output of the integrator circuit according to the output signal of the differentiator circuit, and an output signal from the synchronization detection circuit. a switching circuit that outputs a constant level signal in response to an undetected signal; and a holding circuit that connects the sample circuit and an output terminal of the switching circuit to hold the signal level of the output terminal and use it as the control signal. A phase synchronized circuit comprising: an oscillation output of the voltage controlled oscillator is phase-synchronized with the input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58064753A JPS59190725A (en) | 1983-04-13 | 1983-04-13 | Phase synchronizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58064753A JPS59190725A (en) | 1983-04-13 | 1983-04-13 | Phase synchronizing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59190725A true JPS59190725A (en) | 1984-10-29 |
Family
ID=13267244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58064753A Pending JPS59190725A (en) | 1983-04-13 | 1983-04-13 | Phase synchronizing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59190725A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6298917A (en) * | 1985-10-25 | 1987-05-08 | Nec Corp | Phase synchronizing circuit |
| EP0320748A2 (en) * | 1987-12-18 | 1989-06-21 | BULL HN INFORMATION SYSTEMS ITALIA S.p.A. | Self adjusting phase lock circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4834407A (en) * | 1971-09-07 | 1973-05-18 | ||
| JPS5599840A (en) * | 1979-01-23 | 1980-07-30 | Nec Corp | Phase synchronizing oscillation circuit with sample hold circuit |
| JPS57195311A (en) * | 1981-05-26 | 1982-12-01 | Victor Co Of Japan Ltd | Clock regenerating circuit |
-
1983
- 1983-04-13 JP JP58064753A patent/JPS59190725A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4834407A (en) * | 1971-09-07 | 1973-05-18 | ||
| JPS5599840A (en) * | 1979-01-23 | 1980-07-30 | Nec Corp | Phase synchronizing oscillation circuit with sample hold circuit |
| JPS57195311A (en) * | 1981-05-26 | 1982-12-01 | Victor Co Of Japan Ltd | Clock regenerating circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6298917A (en) * | 1985-10-25 | 1987-05-08 | Nec Corp | Phase synchronizing circuit |
| EP0320748A2 (en) * | 1987-12-18 | 1989-06-21 | BULL HN INFORMATION SYSTEMS ITALIA S.p.A. | Self adjusting phase lock circuit |
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