JPH02280528A - Phase locked loop oscillator - Google Patents
Phase locked loop oscillatorInfo
- Publication number
- JPH02280528A JPH02280528A JP1102662A JP10266289A JPH02280528A JP H02280528 A JPH02280528 A JP H02280528A JP 1102662 A JP1102662 A JP 1102662A JP 10266289 A JP10266289 A JP 10266289A JP H02280528 A JPH02280528 A JP H02280528A
- Authority
- JP
- Japan
- Prior art keywords
- output
- input
- phase
- oscillator
- loop filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims abstract description 11
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 abstract description 4
- 230000010355 oscillation Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は通信機の局部発振器などに用いられる位相同期
発振器に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase synchronized oscillator used as a local oscillator of a communication device.
従来の技術
従来の位相同期発振器は第３図に示すような構成であっ
た。第３図において、入力端子２に加えられる基準信号
と電圧制御発振器アの出力をサンプリング位相比較器１
により位相比較し、サンプリング位相比較器１の出力を
ループフィルタ３に入力し、ループフィルタ３の出力を
分配し、直接、電圧制御発振器７と同期検出器６とスイ
ープ発振器４の入力端子に印加し、電圧制御発振器７の
発振出力端子８から発振出力信号を得、同期検出器６の
同期信号出力端子９から同期出力信号を得、スイープ発
振器４の出力をループフィルタに入力して構成していた
。2. Description of the Related Art A conventional phase-locked oscillator has a configuration as shown in FIG. In Fig. 3, a phase comparator 1 samples the reference signal applied to the input terminal 2 and the output of the voltage controlled oscillator A.
The output of the sampling phase comparator 1 is input to the loop filter 3, and the output of the loop filter 3 is distributed and directly applied to the input terminals of the voltage controlled oscillator 7, synchronization detector 6, and sweep oscillator 4. , an oscillation output signal was obtained from the oscillation output terminal 8 of the voltage controlled oscillator 7, a synchronization output signal was obtained from the synchronization signal output terminal 9 of the synchronization detector 6, and the output of the sweep oscillator 4 was input to the loop filter. .
発明が解決しようとする課題
上記、従来の構成の位相同期発振器では、は期検出器の
入力インピーダンスが高い場合は、同期検出器の影響を
受けずにスイープ発振器は安定に動作するが、同期検出
器のインピーダンスが低いときには、スイープ発振器の
動作が不安定になる欠点があった。Problems to be Solved by the Invention In the phase-locked oscillator with the conventional configuration described above, when the input impedance of the phase detector is high, the sweep oscillator operates stably without being affected by the synchronous detector. When the impedance of the sweep oscillator is low, the operation of the sweep oscillator becomes unstable.
本発明の目的は、従来の欠点を解消し、確実にスイープ
発振させることである。An object of the present invention is to eliminate the conventional drawbacks and reliably perform sweep oscillation.
課題を解決するための手段
本発明の位相同期発振器は、入力基準信号と電圧制御発
振器の出力信号をサンプリング位相比較器で位相比較し
、前記サンプリング位相比較器の出力をループフィルタ
に入力し、前記ループフィルタの出力を分配してスイー
プ発振器とバッフ１アンプに入力し、前記スイープ発振
器の出力を前記ループフィルタに入力し、前記バッフ１
アンプの出力を二分して、前記電圧制御発振器の入力端
子とロック検出器に入力するものである。Means for Solving the Problems The phase synchronized oscillator of the present invention compares the phases of an input reference signal and an output signal of a voltage controlled oscillator with a sampling phase comparator, inputs the output of the sampling phase comparator to a loop filter, and The output of the loop filter is distributed and input to the sweep oscillator and the buffer 1 amplifier, the output of the sweep oscillator is input to the loop filter, and the output of the sweep oscillator is input to the buffer 1 amplifier.
The output of the amplifier is divided into two and input to the input terminal of the voltage controlled oscillator and the lock detector.
作用
上記、技術的手段により、同期検出器の入力インピーダ
ンスが低くても、バッフ１アンプの入力インピーダンス
が高いため、スイープ発振器は同期検出器の影響を受け
ず安定に動作することができる。Effect: With the technical means described above, even if the input impedance of the synchronous detector is low, the input impedance of the buffer 1 amplifier is high, so the sweep oscillator can operate stably without being affected by the synchronous detector.
実施例 本発明の一実施例を第１図に基づいて説明する。Example An embodiment of the present invention will be described based on FIG.
第１図は本発明の位相同期発振器のブロック図である。FIG. 1 is a block diagram of a phase-locked oscillator according to the present invention.
同図において、１はサンプリング位相比較器で、入力端
子２に加えられる入力基準信号と電圧制御発振器７の出
力とを位相比較する。３はループフィルタであり、サン
プリング位相比較器１の出力より雑音や高周波成分を取
シ除いた信号を得る０６はバッフ１アンプであシ入カイ
ンピーダンスが高く、出力インピーダンスが低い。６は
同期検出器であり電圧制御発振器７０入力信号の電圧レ
ベルにより同期状態を判定する。第２図に同期検出器６
の入力部の回路を示す。１ｏは入力端子、１１はダイオ
ード、１２はコンデンサ、１３は抵抗器、１４は第１の
基準電圧、１ｇは第２の基準電圧、１６．１７はオペア
ンプである。ダイオード１１、コンデンサ１２、抵抗器
１３で振幅検波回路を構成し、位相同期回路がスイープ
状態であれば前記振幅検波回路の出力と第２の基準電圧
をオペアンプ１７で比較することによシスイープ状態を
判定している。入力端子１ｏに印加される電圧が負の場
合はダイオード１１が導通し、入力インピーダンスは低
くなる０９は同期信号出力端子であり、８は発振出力端
子である。４はスイープ発振器であり、同期が外れたと
き、発振出力をスイープさせることにより再び同期させ
る。In the figure, reference numeral 1 denotes a sampling phase comparator, which compares the phases of the input reference signal applied to the input terminal 2 and the output of the voltage controlled oscillator 7. 3 is a loop filter which obtains a signal from which noise and high frequency components have been removed from the output of the sampling phase comparator 1. 06 is a buffer 1 amplifier which has high input impedance and low output impedance. Reference numeral 6 denotes a synchronization detector which determines the synchronization state based on the voltage level of the input signal to the voltage controlled oscillator 70. Figure 2 shows the synchronization detector 6.
The circuit of the input section is shown. 1o is an input terminal, 11 is a diode, 12 is a capacitor, 13 is a resistor, 14 is a first reference voltage, 1g is a second reference voltage, and 16.17 is an operational amplifier. A diode 11, a capacitor 12, and a resistor 13 constitute an amplitude detection circuit, and if the phase synchronization circuit is in a sweep state, an operational amplifier 17 compares the output of the amplitude detection circuit with a second reference voltage to detect a sweep state. Judging. When the voltage applied to the input terminal 1o is negative, the diode 11 becomes conductive and the input impedance becomes low. 09 is a synchronization signal output terminal, and 8 is an oscillation output terminal. 4 is a sweep oscillator which, when synchronization is lost, sweeps the oscillation output to synchronize again.
次に動作を説明する。同期検出器６の入力回路が図２に
示される回路であシ、入力インピーダンスが低いときで
も、バッフ１アンプの出力インピーダンスが低いため、
コンデンサ１２を充電するのに十分な電流が供給できる
。またバッフ１アンプ６の入力インピーダンスが高いた
めループフィルタ３の出力電圧はバッフ１アンプ５の影
響を受けることはない。したがってスイープ発振器４は
変化せず安定に動作する。Next, the operation will be explained. If the input circuit of the synchronous detector 6 is the circuit shown in FIG. 2, even when the input impedance is low, the output impedance of the buffer 1 amplifier is low.
Sufficient current can be supplied to charge the capacitor 12. Furthermore, since the input impedance of the buffer 1 amplifier 6 is high, the output voltage of the loop filter 3 is not affected by the buffer 1 amplifier 5. Therefore, the sweep oscillator 4 does not change and operates stably.
発明の効果
本発明によれば、きわめて簡単な回路構成で、スィーブ
回路の動０作を安定させることができ、その実用上の効
果はきわめて大である。Effects of the Invention According to the present invention, the zero operation of the sweep circuit can be stabilized with an extremely simple circuit configuration, and its practical effects are extremely large.
第１図は本発明の一実施例における位相同期発振器のブ
ロック図、第２図は本発明の位相同期発振器に用いられ
る同期検出器の入力回路図、第３図は従来の位相同期発
振器のプリ１２図である。
１・・・・・・サンプリング位相比較器、２・山・・入
力端子、３・・・・・・ループフィルタ、４・・・・・
・スイープ発振器、６・・・・・・バッファアンプ、６
・・・・・・同期検出器、７・・・・・・電圧制御発振
器、８・・・・・・発振出力端子、９・・・・・・同期
信号出力端子。
代理人の氏名 弁理士 粟 野 重 孝 ＃１か１名落
図FIG. 1 is a block diagram of a phase-locked oscillator according to an embodiment of the present invention, FIG. 2 is an input circuit diagram of a synchronization detector used in the phase-locked oscillator of the present invention, and FIG. 3 is a block diagram of a conventional phase-locked oscillator. This is Figure 12. 1...Sampling phase comparator, 2...Input terminal, 3...Loop filter, 4...
・Sweep oscillator, 6...Buffer amplifier, 6
... Synchronization detector, 7 ... Voltage controlled oscillator, 8 ... Oscillation output terminal, 9 ... Synchronization signal output terminal. Name of agent: Patent attorney Shigetaka Awano #1 or 1 person missing
Claims (1)
グ位相比較器で位相比較し、前記サンプリング位相比較
器の出力をループフィルタに入力し、前記ループフィル
タの出力を分配してスイープ発振器とバッファアンプに
入力し、前記スイープ発振器の出力を前記ループフィル
タに入力し、前記バッファアンプの出力を二分して、前
記電圧制御発振器とロック検出器に入力することを特徴
とする位相同期発振器。The input reference signal and the output signal of the voltage controlled oscillator are phase-compared by a sampling phase comparator, the output of the sampling phase comparator is input to a loop filter, and the output of the loop filter is distributed and input to the sweep oscillator and buffer amplifier. A phase synchronized oscillator characterized in that the output of the sweep oscillator is input to the loop filter, and the output of the buffer amplifier is divided into two and input to the voltage controlled oscillator and the lock detector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1102662A JPH02280528A (en) | 1989-04-21 | 1989-04-21 | Phase locked loop oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1102662A JPH02280528A (en) | 1989-04-21 | 1989-04-21 | Phase locked loop oscillator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02280528A true JPH02280528A (en) | 1990-11-16 |
Family
ID=14333447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1102662A Pending JPH02280528A (en) | 1989-04-21 | 1989-04-21 | Phase locked loop oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02280528A (en) |
-
1989
- 1989-04-21 JP JP1102662A patent/JPH02280528A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04313081A (en) | Phase-locked time base circuit | |
| US4068181A (en) | Digital phase comparator | |
| CA1152581A (en) | Phase comparison circuit | |
| JPH10261957A (en) | Pll circuit | |
| JPH02280528A (en) | Phase locked loop oscillator | |
| US4486717A (en) | Phase controlled oscillator including a phase lock loop and dual sweep oscillators | |
| US6008693A (en) | FM-sound demodulator for TV sound signals and method of detecting sound carriers | |
| JP2743133B2 (en) | Phase detector | |
| US5099213A (en) | Phase-locked oscillator with phase lock detection circuit | |
| JP4126782B2 (en) | Phase synchronization circuit and electronic apparatus equipped with the same | |
| JP3712141B2 (en) | Phase-locked loop device | |
| JP2516972Y2 (en) | Phase-locked oscillator | |
| JPS63276921A (en) | Pll circuit | |
| JPH022217A (en) | Phase lock detection circuit | |
| JPS59190725A (en) | Phase synchronizing circuit | |
| JP2503619B2 (en) | Phase lock loop device | |
| KR910008999Y1 (en) | Mode distinctive circuit of pll | |
| KR0122005B1 (en) | Multi frequency modulation phase locked loop detection apparatus | |
| JPH05129947A (en) | Phase locked loop circuit device | |
| JPS59225617A (en) | Phase locked loop | |
| JPH089937Y2 (en) | Digital phase synchronization circuit | |
| JPH0427215A (en) | Pll circuit | |
| JPH0458614A (en) | Pll synthesizer | |
| JPH03217124A (en) | Phase locked loop circuit | |
| JPS60170326A (en) | Phase locked circuit |