JPS5599840A - Phase synchronizing oscillation circuit with sample hold circuit - Google Patents

Phase synchronizing oscillation circuit with sample hold circuit

Info

Publication number
JPS5599840A
JPS5599840A JP695079A JP695079A JPS5599840A JP S5599840 A JPS5599840 A JP S5599840A JP 695079 A JP695079 A JP 695079A JP 695079 A JP695079 A JP 695079A JP S5599840 A JPS5599840 A JP S5599840A
Authority
JP
Japan
Prior art keywords
input signal
hold
incoming
lpf
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP695079A
Other languages
Japanese (ja)
Inventor
Yoshihiro Yamamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP695079A priority Critical patent/JPS5599840A/en
Publication of JPS5599840A publication Critical patent/JPS5599840A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Abstract

PURPOSE:To enable good holding characteristics, by giving the frequency output immediately before the interruption of input signal to the voltage controlled oscillator and keeping the hold capacitance as that of LPF, if no input signal is incoming. CONSTITUTION:The input signal fIN in burst shape is frequency-divided with the frequency division circuit 1/N, and the frequency division signal is differentiated d/dt. Further, when the input signal is incoming, the sampled voltage is fed to the buffer circuit A via LPF and oscillation VCO is made with the average current. Next, if no input signal is incoming, the sampling signal is not produced, the switch SW keeps open state, and the oscillator VCO performs the output corresponding to the voltage stored in the hold battery until the next sampling signal is taken place. Thus, the frequency output immediately before the input signal interruption is obtained, the hold capacity is equal to the capacitance of LPF and greater than the capacity of hold battery, allowing to obtain best holding characteristics.
JP695079A 1979-01-23 1979-01-23 Phase synchronizing oscillation circuit with sample hold circuit Pending JPS5599840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP695079A JPS5599840A (en) 1979-01-23 1979-01-23 Phase synchronizing oscillation circuit with sample hold circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP695079A JPS5599840A (en) 1979-01-23 1979-01-23 Phase synchronizing oscillation circuit with sample hold circuit

Publications (1)

Publication Number Publication Date
JPS5599840A true JPS5599840A (en) 1980-07-30

Family

ID=11652500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP695079A Pending JPS5599840A (en) 1979-01-23 1979-01-23 Phase synchronizing oscillation circuit with sample hold circuit

Country Status (1)

Country Link
JP (1) JPS5599840A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59190725A (en) * 1983-04-13 1984-10-29 Nec Corp Phase synchronizing circuit
US5107227A (en) * 1988-02-08 1992-04-21 Magellan Corporation (Australia) Pty. Ltd. Integratable phase-locked loop

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59190725A (en) * 1983-04-13 1984-10-29 Nec Corp Phase synchronizing circuit
US5107227A (en) * 1988-02-08 1992-04-21 Magellan Corporation (Australia) Pty. Ltd. Integratable phase-locked loop

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