JPS6331985B2 - - Google Patents

Info

Publication number
JPS6331985B2
JPS6331985B2 JP56189548A JP18954881A JPS6331985B2 JP S6331985 B2 JPS6331985 B2 JP S6331985B2 JP 56189548 A JP56189548 A JP 56189548A JP 18954881 A JP18954881 A JP 18954881A JP S6331985 B2 JPS6331985 B2 JP S6331985B2
Authority
JP
Japan
Prior art keywords
circuit
sampling
sampling phase
phase error
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56189548A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5890854A (ja
Inventor
Hideo Suzuki
Shunsuke Yoda
Meiki Yahata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP56189548A priority Critical patent/JPS5890854A/ja
Publication of JPS5890854A publication Critical patent/JPS5890854A/ja
Publication of JPS6331985B2 publication Critical patent/JPS6331985B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
JP56189548A 1981-11-26 1981-11-26 サンプリング位相同期回路 Granted JPS5890854A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56189548A JPS5890854A (ja) 1981-11-26 1981-11-26 サンプリング位相同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56189548A JPS5890854A (ja) 1981-11-26 1981-11-26 サンプリング位相同期回路

Publications (2)

Publication Number Publication Date
JPS5890854A JPS5890854A (ja) 1983-05-30
JPS6331985B2 true JPS6331985B2 (fr) 1988-06-28

Family

ID=16243153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56189548A Granted JPS5890854A (ja) 1981-11-26 1981-11-26 サンプリング位相同期回路

Country Status (1)

Country Link
JP (1) JPS5890854A (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618366B2 (ja) * 1985-02-28 1994-03-09 日本電気株式会社 変復調装置のタイミング再生回路
JPH01274548A (ja) * 1988-04-26 1989-11-02 Nec Corp 復調装置
FR2888187B1 (fr) * 2005-07-08 2008-10-10 Peugeot Citroen Automobiles Sa Dispositif d'essuyage d'une vitre d'automobile comportant un balai d'essuie-glace a deplacement lineaire.
JP2013126224A (ja) * 2011-12-16 2013-06-24 Nec Engineering Ltd クロックリカバリ回路、これを含むデジタル復調回路、クロックリカバリ方法及びこれを含むデジタル復調方法

Also Published As

Publication number Publication date
JPS5890854A (ja) 1983-05-30

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