JPS63318765A - Structure of capacitor for integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to reduce the area in the horizontal direction and to reduce the chip area when a capacitor of the same capacity is formed, by forming unevenness on a substrate or on the oxide film on the substrate and forming a capacitor on the unevenness. CONSTITUTION:A capacitor is formed on the unevenness formed on a substrate 1 or on the oxide film 2 on the substrate 1. For instance, a slant face having an angle of 45 deg. is formed on an LOCOS film 2 formed on a wafer with a taper etching liquid consisting of hydrogen fluoride and ammonium fluoride. 3000-5000Angstrom of polycrystalline silicon is depositioned on the LOCOS film 2 formed in this way, therein phosphorus is diffused followed by performing patterning so as to be made the lower part electrode 3 of a capacitor. The polycrystalline silicon is oxidized at 900 deg.C-1000 deg.C to form an oxide film 4 of 500-1000Angstrom . Thereon, again the polycrystalline silicon is deposited at 3000-5000Angstrom and phosphorous is diffused followed by performing patterning to be made the upper electrode 5 of the capacitor.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention was inspired by the structure of capacitors on wafers,
In particular, it inspired the improvement of capacitors that use polysilicon as electrodes.

[Summary of the invention]

In a method of forming a polysilicon capacitor on a wafer, the area of the polysilicon electrode is increased by forming the lower layer polysilicon electrode on top of the unevenness,
When forming a capacitor with the same capacity as a conventional capacitor, the lateral area is reduced, making it possible to reduce the chip area.

[Conventional technology]

The conventional method of forming a polysilicon capacitor is shown in Figure 2.
The structure was as shown in .

That is, an oxide film for insulation isolation (L
Polycrystalline silicon 3 containing a high concentration of impurities is formed on OGO 3) 2 to form a lower electrode of a capacitor, and this polycrystalline silicon is oxidized to form a dielectric layer 4. Next, polycrystalline silicon 5 containing impurities at a high concentration is formed and patterned.

Since the capacitance of a capacitor is determined by the facing area, this patterning determines the capacitance.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional technology, in order to form a capacitor with a desired large capacity, the oxide film 4 is made thinner, or a film with a different dielectric constant, such as a silicon nitride film, is used. This necessitates the use of silicon, which has a large surface area, and prevents the manufacture of semiconductor devices using technologies such as switched capacitor filters with large chip areas and at low cost.

[Means for solving problems]

The capacitor structure for an integrated circuit according to the present invention is characterized in that unevenness is formed on a substrate or an oxide film on the substrate, and a capacitor is formed on the unevenness.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of the present invention. 0.7~1°6μm LOG formed on wafer 1
A slope with an angle of 45@ is formed on the O8 film using a tapered etchant consisting of hydrofluoric acid and ammonium fluoride. 56 layers of polycrystalline silicon are placed on top of the LOGO32 thus created.
Deposit 3000-5000 λ at a temperature of 0@C to 630 aC. Add 10” to 10”/cm of phosphorus to this.
Then, a resist is applied and patterned to form the lower electrode 3 of the capacitor.
This polycrystalline silicon is oxidized at 900°C to 1000''C to form an oxide film 4 of 500 to 1000 layers. On top of this, polycrystalline silicon is applied again at 580＠C to 630°C.
3,000 to 5,000 people are deposited at a temperature of 3,000 to 5,000 to diffuse phosphorus at a concentration of 1,011 to 10''/cm. Next, a resist is applied and patterned to form the upper electrode 5 of the capacitor. The figure is a cross-sectional view showing another embodiment of the present invention.'LOCO3If12 of 0.7 to 1.6 μm formed on the wafer 1 is anisotropically etched by reactive ion etching (RIE). to form a step of 0.2 to 0.7 μm.

LOGO3II thus formed! ! 2, polycrystalline silicon was heated to 300°C at a temperature of 5606°C to 630°C.
Deposit about 0 to 5000λ. Add 1 phosphorus to this
Diffuses at a concentration of 0'-108''/cm''. Next, a resist is applied and patterned to form the lower electrode 3 of the capacitor. This polycrystalline silicon was heated to 90”C.
Oxidation is performed at ~1100°C to form an oxide film 4 of 500 to 1000 layers. On top of this, add 5 layers of polycrystalline silicon again.
Deposit 3,000 to 5,000 people at a concentration of 60° to 630°C, and deposit phosphorus at 1,011 to 10'''/cm.
Diffuse to a concentration of 3. Next, a resist is applied and patterned to form the upper electrode 5 of the capacitor.

(Effects of the Invention) As described above, by making the structure of the present invention, compared to making a capacitor on the plane of LOGO3, it is possible to make a capacitor with a large capacity by effectively using the lateral area of LOGO3. Alternatively, if the capacity is the same, the area can be reduced, the chip area can be reduced, and the cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a main sectional view of an integrated circuit capacitor showing an embodiment of the present invention. FIG. 2 is a main sectional view showing a conventional capacitor for integrated circuits. FIG. 3 is a main sectional view of a capacitor for integrated circuits showing another embodiment of the present invention. 1... Wafer 2... Oxide film for insulation isolation (LOGO3) 3... Polycrystalline silicon 4... Oxide film 5... Polycrystalline silicon or more

Claims (1)

[Claims] A structure of a capacitor for an integrated circuit, characterized by having a capacitor formed on a substrate or an uneven surface formed on an oxide film on a substrate.