JPH09270498A - Manufacture of semiconductor memory device - Google Patents

Manufacture of semiconductor memory device

Info

Publication number
JPH09270498A
JPH09270498A JP8103753A JP10375396A JPH09270498A JP H09270498 A JPH09270498 A JP H09270498A JP 8103753 A JP8103753 A JP 8103753A JP 10375396 A JP10375396 A JP 10375396A JP H09270498 A JPH09270498 A JP H09270498A
Authority
JP
Japan
Prior art keywords
film
silicon oxide
silicon
oxide film
poly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8103753A
Other languages
Japanese (ja)
Inventor
Kohei Eguchi
公平 江口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP8103753A priority Critical patent/JPH09270498A/en
Publication of JPH09270498A publication Critical patent/JPH09270498A/en
Withdrawn legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a silicon nitride film from being locally broken by a method wherein the surface of a first polycrystalline silicon film is thermally oxidized for the formation of a first silicon oxide film, the oxide film is removed, a silicon nitride film is formed, and a second silicon oxide and a second polycrystalline silicon are laminated thereon. SOLUTION: A first ground polysilicon film 2 is formed on a semiconductor substrate 1 through the intermediary of a silicon oxide film 11, and the surface of the ground polysilicon film is thermally oxidized for the formation of a first silicon oxide film 6. Then, the first silicon oxide film 6 is removed, when the pattern edge of the first ground polysilicon film 2 is rounded by trimming. A silicon nitride film 3 is formed on the first ground polysilicon film 2, and a second silicon oxide film 4 is formed thereon. Furthermore, a second polysilicon film 5 is formed on the second silicon oxide film 4. By this setup, the silicon nitride film 3 can be prevented from being locally broken, and a semiconductor memory device of this constitution can be ensured of a high capacity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体記憶装置の製
造方法に関し、例えば、DRAMに含まれる容量素子の
製造方法に適用して特に好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and is particularly suitable for application to, for example, a method of manufacturing a capacitive element included in a DRAM.

【0002】[0002]

【従来の技術】DRAMにおける容量素子には、通常、
下部及び上部電極にPoly−Siが、また、誘電体膜にS
iN膜及びその表面を酸化することによりSiO2 に変
化させた膜が用いられている。容量を上げるためには、
誘電体膜としてSiO2 より誘電率の高いSiNのみを
用いる方が有利であるが、SiN膜のみではリーク電流
が高く、また、電気的耐圧も低くなるため、SiN膜表
面を酸化することにより、これを防いでいる。
2. Description of the Related Art Generally, a capacitive element in a DRAM is
Poly-Si is used for the lower and upper electrodes, and S is used for the dielectric film.
An iN film and a film converted to SiO 2 by oxidizing the surface thereof are used. To increase the capacity,
It is advantageous to use only SiN having a higher dielectric constant than SiO 2 as the dielectric film, but the SiN film alone has a high leak current and a low electric breakdown voltage. Therefore, by oxidizing the SiN film surface, It prevents this.

【0003】このような容量素子の従来の製造方法を図
2を参照して説明する。
A conventional method of manufacturing such a capacitive element will be described with reference to FIG.

【0004】まず、図2(a)に示すように、不図示の
基板上に形成された下地絶縁膜11上に、容量素子の下
部電極となるPoly−Si膜2をパターン形成する。
First, as shown in FIG. 2A, a Poly-Si film 2 to be a lower electrode of a capacitor is patterned on a base insulating film 11 formed on a substrate (not shown).

【0005】次いで、図2(b)に示すように、化学的
気相成長法(CVD法)によりSiN膜3を通常50〜
100Åの膜厚に形成する。
Next, as shown in FIG. 2 (b), the SiN film 3 is usually formed by a chemical vapor deposition method (CVD method) to a thickness of 50 to 50 nm.
It is formed to a film thickness of 100Å.

【0006】次いで、図2(c)に示すように、熱酸化
を施すことによりSiN膜3の表面を通常20Å前後の
膜厚でSiO2 膜4に変化させる。
Next, as shown in FIG. 2C, the surface of the SiN film 3 is changed to the SiO 2 film 4 with a film thickness of usually about 20Å by performing thermal oxidation.

【0007】次いで、図2(d)に示すように、容量素
子の上部電極となるPoly−Si膜5を形成する。
Next, as shown in FIG. 2 (d), a Poly-Si film 5 to be an upper electrode of the capacitive element is formed.

【0008】[0008]

【発明が解決しようとする課題】従来は、SiN膜3を
薄膜化した場合、SiN膜3表面を酸化する際に、図3
に示すように、局部的にSiN膜3が破れることによ
り、局部的に厚いSiO2膜36が形成され、その結
果、容量値が所望の値に達しないという問題があった。
このSiN膜3が局部的に破れる部分は、図示の如く、
下部電極Poly−Si膜2のパターンエッジであることが
分かっている。これは、エッジ部に応力が集中するため
と推定される。
Conventionally, when the SiN film 3 is thinned, when the surface of the SiN film 3 is oxidized, as shown in FIG.
As shown in FIG. 5, the SiN film 3 is locally broken, so that a thick SiO 2 film 36 is locally formed, and as a result, there is a problem that the capacitance value does not reach a desired value.
The portion where the SiN film 3 is locally broken is, as shown in the figure,
It is known that this is the pattern edge of the lower electrode Poly-Si film 2. It is estimated that this is because stress concentrates on the edge portion.

【0009】そこで、この発明は、例えば、SiN膜を
薄くしていっても下部電極Poly−Si膜のパターンエッ
ジでのSiN膜表面酸化時のSiN膜の局部的破れを防
ぐことにより、より高い容量値の容量素子を備えた半導
体装置の製造方法を提供することを目的とする。
Therefore, the present invention is further improved by preventing local breakage of the SiN film at the time of oxidation of the surface of the SiN film at the pattern edge of the lower electrode Poly-Si film even if the SiN film is thinned. An object of the present invention is to provide a method for manufacturing a semiconductor device including a capacitance element having a capacitance value.

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に第1の多結晶シリコン膜を形
成し、この第1の多結晶シリコン膜をキャパシタの下部
電極パターンに加工する第1の工程と、前記第1の多結
晶シリコン膜表面を熱酸化して前記第1の多結晶シリコ
ン膜上に第1のシリコン酸化膜を形成する第2の工程
と、前記第1のシリコン酸化膜を除去する第3の工程
と、前記第1の多結晶シリコン膜上にシリコン窒化膜を
形成する第4の工程と、前記シリコン窒化膜上に第2の
シリコン酸化膜を形成する第5の工程と、前記第2のシ
リコン酸化膜上に第2の多結晶シリコン膜を形成する第
6の工程とを有する。
According to a method of manufacturing a semiconductor device of the present invention, a first polycrystalline silicon film is formed on a semiconductor substrate, and the first polycrystalline silicon film is processed into a lower electrode pattern of a capacitor. And a second step of thermally oxidizing the surface of the first polycrystalline silicon film to form a first silicon oxide film on the first polycrystalline silicon film, A third step of removing the silicon oxide film, a fourth step of forming a silicon nitride film on the first polycrystalline silicon film, and a second step of forming a second silicon oxide film on the silicon nitride film. 5 and a sixth step of forming a second polycrystalline silicon film on the second silicon oxide film.

【0011】本発明の一態様では、前記第3の工程にお
いて、弗酸を用いて前記第1のシリコン酸化膜を除去す
る。
In one aspect of the present invention, in the third step, the first silicon oxide film is removed using hydrofluoric acid.

【0012】本発明の一態様では、前記第3の工程にお
いて、弗素系プラズマを用いて前記第1のシリコン酸化
膜を除去する。
In one aspect of the present invention, in the third step, the first silicon oxide film is removed by using fluorine plasma.

【0013】[0013]

【作用】本発明においては、例えば、キャパシタの下部
電極としてのPoly−Si膜パターン形成工程とSiN膜
形成工程との間で一度Poly−Si膜表面を酸化し、次い
で、そのPoly−Si膜表面に形成されたSiO2 膜を除
去する。
In the present invention, for example, the surface of the Poly-Si film is oxidized once between the step of forming the pattern of the Poly-Si film as the lower electrode of the capacitor and the step of forming the SiN film, and then the surface of the Poly-Si film is oxidized. The SiO 2 film formed on the substrate is removed.

【0014】即ち、例えば、Poly−Si膜で下部電極パ
ターン形成後、そのPoly−Si膜表面の熱酸化を行う。
この時、Poly−Si膜パターンエッジ部においては、Po
ly−Si膜を上面及び側面から酸化が進行してくるた
め、未酸化のPoly−Si部分はほぼ90°の鋭い角から
丸みを有した形状に変化する。従って、この後、Poly−
Si膜表面のSiO2 膜を除去した跡に形成されるSi
N膜の下地には鋭いPoly−Si膜の角がなくなってい
る。
That is, for example, after the lower electrode pattern is formed of the Poly-Si film, the surface of the Poly-Si film is thermally oxidized.
At this time, in the edge portion of the Poly-Si film pattern, Po
Oxidation proceeds from the upper surface and the side surfaces of the ly-Si film, so that the unoxidized Poly-Si portion changes from a sharp angle of about 90 ° to a rounded shape. Therefore, after this, Poly−
Si formed after the SiO 2 film on the surface of the Si film is removed
There is no sharp corner of the Poly-Si film under the N film.

【0015】この結果、その後のSiN膜表面の酸化工
程においてPoly−Si膜パターンエッジでのSiN膜の
応力集中が緩和されるため、局部的SiN膜破れが発生
しにくくなる。
As a result, stress concentration of the SiN film at the edge of the poly-Si film pattern is relaxed in the subsequent step of oxidizing the surface of the SiN film, so that local SiN film breakage is less likely to occur.

【0016】[0016]

【発明の実施の形態】以下、図1を用いて本発明の第1
の実施の形態によるDRAMの容量素子の形成方法を説
明する。
BEST MODE FOR CARRYING OUT THE INVENTION The first embodiment of the present invention will be described below with reference to FIG.
A method of forming the capacitive element of the DRAM according to the embodiment will be described.

【0017】まず、図1(a)に示すように、シリコン
半導体基板1上に形成されたSiO2 膜11上に第1の
Poly−Si膜2をCVD法により膜厚5000Å程度に
形成し、更に、所望のキャパシタの下部電極パターンに
パターニングする。
First, as shown in FIG. 1A, a first film is formed on the SiO 2 film 11 formed on the silicon semiconductor substrate 1.
A Poly-Si film 2 is formed by a CVD method to a film thickness of about 5000 Å, and is further patterned into a desired lower electrode pattern of a capacitor.

【0018】次いで、図1(b)に示すように、酸化雰
囲気中で900℃の熱処理を施すことにより、Poly−S
i膜2の表面から厚さ500Å程度の部分を酸化し、S
iO2 膜6を形成する。
Then, as shown in FIG. 1B, a heat treatment is performed at 900 ° C. in an oxidizing atmosphere to give Poly-S.
Oxide a portion of the thickness of about 500Å from the surface of the i film 2
The iO 2 film 6 is formed.

【0019】次いで、図1(c)に示すように、HF溶
液を用いてPoly−Si膜2表面のSiO2 膜6を除去す
る。この時、Poly−Si膜2のパターンエッジは初期の
状態に比べて丸みを有したいわゆる縁取りされた形状と
なっている。
Next, as shown in FIG. 1C, the SiO 2 film 6 on the surface of the Poly-Si film 2 is removed using an HF solution. At this time, the pattern edge of the Poly-Si film 2 has a rounded shape compared to the initial state, that is, a so-called edged shape.

【0020】次いで、図1(d)に示すように、CVD
法によりSiN膜3を50Å程度の膜厚に形成する。
Then, as shown in FIG. 1D, CVD
The SiN film 3 is formed to a film thickness of about 50Å by the method.

【0021】次いで、図1(e)に示すように、酸素雰
囲気中で900℃の熱処理を行うことにより、SiN膜
3の表面から厚さ20Å程度の部分を酸化し、SiO2
膜4を形成する。
Then, as shown in FIG. 1 (e), a heat treatment at 900 ° C. is performed in an oxygen atmosphere to oxidize a portion of the SiN film 3 having a thickness of about 20 Å from the surface thereof, and SiO 2
The film 4 is formed.

【0022】次いで、図1(f)に示すように、キャパ
シタの上部電極となる第2のPoly−Si膜5を形成す
る。
Next, as shown in FIG. 1F, a second Poly-Si film 5 which will be the upper electrode of the capacitor is formed.

【0023】この第1の実施の形態では、図1(b)〜
(c)の工程を経る結果、第1のPoly−Si膜2のパタ
ーンエッジ部でのSiN膜3の局部的破れはなくなり、
容量素子の容量値低下は認められなかった。
In the first embodiment, as shown in FIG.
As a result of going through the step (c), local breakage of the SiN film 3 at the pattern edge portion of the first Poly-Si film 2 is eliminated,
No decrease in the capacitance value of the capacitive element was observed.

【0024】次に、本発明の第2の実施の形態について
説明する。
Next, a second embodiment of the present invention will be described.

【0025】この第2の実施の形態の工程断面図は、上
述した第1の実施の形態と実質的に同じであるため、そ
の図示を省略するが、この第2の実施の形態において
は、図1(c)に示す第1のPoly−Si膜2の表面に形
成されたSiO2 膜6を除去する方法として、F系ガス
を用いたプラズマによるドライエッチングを用いる。即
ち、エッチング装置として平行平板型エッチャー(不図
示)を用い、F系ガスとして、CF4 とO2 の混合ガス
を用いる。
The process sectional view of the second embodiment is substantially the same as that of the above-described first embodiment, and therefore the illustration thereof is omitted, but in the second embodiment, As a method of removing the SiO 2 film 6 formed on the surface of the first Poly-Si film 2 shown in FIG. 1C, dry etching using plasma using F-based gas is used. That is, a parallel plate type etcher (not shown) is used as an etching device, and a mixed gas of CF 4 and O 2 is used as an F-based gas.

【0026】[0026]

【発明の効果】本発明によれば、容量素子の誘電体膜の
一部に用いるSiN膜のリーク電流対策及び耐圧劣化対
策のためのSiN膜表面の酸化工程において、SiN膜
の局部的破れによって生じる容量値の低下を防ぐことが
でき、高歩留りの半導体装置の製造方法を実現できる。
According to the present invention, due to the local breakage of the SiN film in the oxidation process of the surface of the SiN film as a measure against the leak current and the withstand voltage deterioration of the SiN film used as a part of the dielectric film of the capacitive element. It is possible to prevent the resulting decrease in the capacitance value and realize a method for manufacturing a semiconductor device with a high yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施形態による容量素子の製造方法
を示す工程断面図である。
FIG. 1 is a process cross-sectional view showing a method of manufacturing a capacitive element according to an embodiment of the present invention.

【図2】従来の容量素子の製造方法を示す工程断面図で
ある。
2A to 2D are process cross-sectional views showing a conventional method of manufacturing a capacitive element.

【図3】従来の問題点を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing a conventional problem.

【符号の説明】[Explanation of symbols]

1 シリコン半導体基板 2 Poly−Si膜(下部電極) 3 SiN膜 4 SiO2 膜 5 Poly−Si膜(上部電極) 6 SiO2 膜 11 SiO2 1 Silicon Semiconductor Substrate 2 Poly-Si Film (Lower Electrode) 3 SiN Film 4 SiO 2 Film 5 Poly-Si Film (Upper Electrode) 6 SiO 2 Film 11 SiO 2 Film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に第1の多結晶シリコン膜
を形成し、この第1の多結晶シリコン膜をキャパシタの
下部電極パターンに加工する第1の工程と、 前記第1の多結晶シリコン膜表面を熱酸化して前記第1
の多結晶シリコン膜上に第1のシリコン酸化膜を形成す
る第2の工程と、 前記第1のシリコン酸化膜を除去する第3の工程と、 前記第1の多結晶シリコン膜上にシリコン窒化膜を形成
する第4の工程と、 前記シリコン窒化膜上に第2のシリコン酸化膜を形成す
る第5の工程と、 前記第2のシリコン酸化膜上に第2の多結晶シリコン膜
を形成する第6の工程とを有することを特徴とする半導
体記憶装置の製造方法。
1. A first step of forming a first polycrystalline silicon film on a semiconductor substrate and processing the first polycrystalline silicon film into a lower electrode pattern of a capacitor, the first polycrystalline silicon film. The first surface is formed by thermally oxidizing the film surface.
A second step of forming a first silicon oxide film on the polycrystalline silicon film, a third step of removing the first silicon oxide film, and a silicon nitride film on the first polycrystalline silicon film. A fourth step of forming a film, a fifth step of forming a second silicon oxide film on the silicon nitride film, and a second polycrystalline silicon film on the second silicon oxide film And a sixth step, which is a method for manufacturing a semiconductor memory device.
【請求項2】 前記第3の工程において、弗酸を用いて
前記第1のシリコン酸化膜を除去することを特徴とする
請求項1に記載の半導体記憶装置の製造方法。
2. The method of manufacturing a semiconductor memory device according to claim 1, wherein in the third step, the first silicon oxide film is removed using hydrofluoric acid.
【請求項3】 前記第3の工程において、弗素系プラズ
マを用いて前記第1のシリコン酸化膜を除去することを
特徴とする請求項1に記載の半導体記憶装置の製造方
法。
3. The method of manufacturing a semiconductor memory device according to claim 1, wherein in the third step, the first silicon oxide film is removed using a fluorine-based plasma.
JP8103753A 1996-03-29 1996-03-29 Manufacture of semiconductor memory device Withdrawn JPH09270498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8103753A JPH09270498A (en) 1996-03-29 1996-03-29 Manufacture of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8103753A JPH09270498A (en) 1996-03-29 1996-03-29 Manufacture of semiconductor memory device

Publications (1)

Publication Number Publication Date
JPH09270498A true JPH09270498A (en) 1997-10-14

Family

ID=14362326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8103753A Withdrawn JPH09270498A (en) 1996-03-29 1996-03-29 Manufacture of semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH09270498A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046489A (en) * 1997-05-29 2000-04-04 Nec Corporation Capacitor with high-dielectric-constant dielectric and thick electrode and fabrication method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046489A (en) * 1997-05-29 2000-04-04 Nec Corporation Capacitor with high-dielectric-constant dielectric and thick electrode and fabrication method thereof

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