JPS63316152A - Synchronous bus controller - Google Patents

Abstract

PURPOSE:To facilitate the control of a synchronous bus, by operating a bus arbitration circuit by an independent clock different from the basic clock of a bus user. CONSTITUTION:Users A10 and B20 send bus usage right requests 101 and 201 to a bus arbitration part 40 at the time of using a bus. The arbitration part 40, after taking synchronization at synchronization circuits C44 and D45 by using the clock 603, performs arbitration at an arbitration circuit 41, and sends but usage rights 401 and 402 by synchronizing the usage right 401 with the clock 601 by a synchronization circuit A42 and synchronizing the usage right 402 with the clock 602 by a synchronization circuit B43. The user A10 receiving the usage right 401 performs data transfer between a resource C30 via a bus 501 synchronizing with the clock 601. Similarly, the data transfer between the user B20 and the resource C30 is performed synchronously with the clock 602.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a control device for a synchronous data transfer bus.

〔overview〕

The present invention provides a synchronous data transfer bus control device that includes a bus arbitration circuit that operates with an independent clock that is different from the basic clock of a plurality of bus users, so that each user and resource can have a synchronous circuit between them and the bus. This makes it easy to control a synchronous bus.

[Conventional technology]

Conventionally, in this type of synchronous data transfer bus control method, data transfer is performed after specifying the clock on the bus.
All operations on the bus occur in complete synchronization with the bus.

A bus using this method will operate efficiently if all users and resources using the bus operate with the bus clock, but if each user operates with a different clock, each user will I had to install a synchronization circuit between myself and the bus using my own clock and the bus's clock.

[Problems that the originating station attempts to solve]

However, for a small-scale bus such as an internal bus that is closed within a device, having a synchronous circuit has a large impact in terms of circuit scale, and also causes deterioration in performance. On the other hand, if we take a human output controller connected to a memory bus as an example, users of the internal bus include the processor, memory bus connection control unit, etc., but these are basically independent Due to the design, there are many cases where the basic clocks used are different. For small-scale buses such as internal buses that are closed within devices, the number of connected users, resources, and functions are limited, so a simpler synchronous bus method has been required. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a device that can solve these problems and easily control a synchronous bus without requiring each user or resource to have a synchronous circuit between them and the bus. do.

[Means for solving problems]

The present invention provides a plurality of bus users each operating with a different basic clock, one or more bus resources accessed by the plurality of bus users and inputting the basic clock used by the bus users, and the bus user and the a bus commonly connected to a bus resource, and receiving requests for bus usage rights from the plurality of bus users;
a bus arbitration circuit that grants the right to use the bus to any one of the plurality of bus users and notifies the bus resource to which one of the plurality of bus users has been granted the right to use the bus; This bus arbitration circuit is characterized in that it operates with a clock independent of the basic clocks of the plurality of bus users.

[Effect]

It operates with an independent clock that is different from the basic clock of multiple bus users, receives bus usage rights requests for the bus from multiple bus users, grants the bus usage rights to any one of the multiple bus users, and Notifies which of a plurality of bus users has been granted the right to use the bus for one or more bus resources.

This function allows users and resources to easily control a synchronous bus without requiring a synchronous circuit between them and the bus.

〔Example〕

Next, a synchronous bus control device according to an embodiment of the present invention will be explained based on the drawings. The figure is a block diagram showing the configuration of a synchronous bus control device according to an embodiment of the present invention.

The synchronous bus control device according to the embodiment of the present invention includes, on the bus 501, a user AIO that operates with a basic clock 601 with a period T1, and a user B 20 that operates with a basic clock 601 with a period T2.
The resource C30 accessed by this user AIO and user B20, and the basic locks 601 and 602
A bus arbitration unit 40 that operates with an independent clock is also connected.

This bus arbitration section 40 includes an arbitration circuit 41 and a synchronous circuit A4.
2. Synchronous circuit B43, synchronized circuit C44 and synchronized circuit D
45.

The operation of the embodiment of the present invention configured as described above will be explained. When the need to use the bus arises, the user AIO and the user B 20 issue a bus usage right request 1 to the bus arbitration unit 40.
Send 01 and 201. The bus arbitration unit 40 uses the clock 603 to synchronize the synchronization circuits C44 and D45, and then performs arbitration in the arbitration circuit 41 to obtain the right to use the bus.
1 and 402 as the bus usage right 401
is sent in synchronization with the clock 601 by the synchronization circuit A42, and the bus usage right 402 is sent in synchronization with the clock 602 by the synchronization circuit B43.

Here, if we send the bus usage right 401 to the user AIO, the user AIO that received the bus usage right 401 will recognize that it has acquired the bus usage right, and the resource C30 will be sent an access from the user °AIO. Know. Thereafter, operations such as data transfer via the bus 501 are performed between the user AIO and the resource C30 in synchronization with the clock 601.

When the user AIO completes the operation with the resource C30,
The bus usage right request 101 is canceled. Bus mediation section 40
In response to this, after synchronizing with the clock 603 in the synchronization circuit C44, it learns that the user AIO does not need the right to use the bus, and cancels the right to use the bus 401 for the user AIO.
Synchronization signal 4 of bus usage right request 201 from user B20
If 51 has been sent, the bus usage right 402 is sent, and if not, the operation is ended.

When the bus usage right 402 is sent to the user B20, the user B20 knows that he has acquired the bus usage right as described above, knows that the resource C30 will be accessed later by the user B20, and then sends the user B20 to the resource C30. Operations such as data transfer are performed between B20 and resource C30 via bus 501 in synchronization with clock 602.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to easily control a synchronous bus without requiring each user and resource to have a synchronous circuit between them and the bus.

[Brief explanation of drawings]

The figure is a block diagram showing the configuration of an embodiment of the present invention. 10... User Δ, 20... User B, 30...
Resource C140...Bus arbitration unit, 41...Arbitration circuit, 42.43.44.45...Synchronization circuit, 101.
201... Bus usage right request, 401.402... Bus usage right, 441.451... Synchronization signal, 501...
・Bus, 601.602...Basic clock, 603・
··clock.

Claims (1)

[Claims] (1) A plurality of bus users each operating with a different basic clock, one or more bus resources that are accessed by the plurality of bus users and input the basic clock used by the bus users, the bus user and the bus A bus that is commonly connected to a resource, and receives a bus usage right request from the plurality of bus users, grants the bus usage right to any one of the plurality of bus users, and provides the bus usage right to the bus resource. and a bus arbitration circuit that notifies which of the plurality of bus users has been granted the right to use the bus, and the bus arbitration circuit is configured to operate with a clock independent of the basic clock of the plurality of bus users. A synchronous bus control device characterized by: