JPS6331575U - - Google Patents
Info
- Publication number
- JPS6331575U JPS6331575U JP12524586U JP12524586U JPS6331575U JP S6331575 U JPS6331575 U JP S6331575U JP 12524586 U JP12524586 U JP 12524586U JP 12524586 U JP12524586 U JP 12524586U JP S6331575 U JPS6331575 U JP S6331575U
- Authority
- JP
- Japan
- Prior art keywords
- multilayer printed
- circuit board
- printed circuit
- conductor circuit
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 1
Description
第１図は本考案の一実施例の断面図、第２図は
実装状態の断面図、第３図は従来構造の断面図で
ある。
１ａ〜１ｆ，１１ａ〜１１ｆ……導体回路層（
１ｄ……接地回路）、２ａ〜２ｅ，１２ａ〜１２
ｅ……絶縁層、３，１３……寸法、４，１４……
金属筐体、５，１５……ボルト。
FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of a mounted state, and FIG. 3 is a sectional view of a conventional structure. 1a to 1f, 11a to 11f...conductor circuit layer (
1d...ground circuit), 2a to 2e, 12a to 12
e... Insulating layer, 3, 13... Dimensions, 4, 14...
Metal casing, 5, 15... bolts.
Claims (1)
した多層プリント基板において、接地回路として
構成される前記導体回路層の周囲の少なくとも一
部を積層方向に露呈させたことを特徴とする多層
プリント基板。 (2) 接地回路としての導体回路層は、複数の導
体回路層の中の内側の導体回路層で構成してなる
実用新案登録請求の範囲第１項記載の多層プリン
ト基板。 (3) 露呈された導体回路層を金属筐体に接触さ
せた状態で多層プリント基板をこの金属筐体に取
着してなる実用新案登録請求の範囲第１項記載の
多層プリント基板。[Claims for Utility Model Registration] (1) In a multilayer printed circuit board in which a plurality of conductor circuit layers and insulating layers are alternately laminated, at least a portion of the periphery of the conductor circuit layer configured as a ground circuit is formed in the lamination direction. A multilayer printed circuit board characterized by being exposed. (2) The multilayer printed circuit board according to claim 1, wherein the conductor circuit layer serving as a ground circuit is constituted by an inner conductor circuit layer among a plurality of conductor circuit layers. (3) The multilayer printed circuit board according to claim 1, wherein the multilayer printed circuit board is attached to a metal casing with the exposed conductor circuit layer in contact with the metal casing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12524586U JPS6331575U (en) | 1986-08-18 | 1986-08-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12524586U JPS6331575U (en) | 1986-08-18 | 1986-08-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331575U true JPS6331575U (en) | 1988-03-01 |
Family
ID=31017978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12524586U Pending JPS6331575U (en) | 1986-08-18 | 1986-08-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331575U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1098287A (en) * | 1996-09-19 | 1998-04-14 | Toshiba Corp | Cooler for circuit board module and portable electronic equipment having the cooler |
-
1986
- 1986-08-18 JP JP12524586U patent/JPS6331575U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1098287A (en) * | 1996-09-19 | 1998-04-14 | Toshiba Corp | Cooler for circuit board module and portable electronic equipment having the cooler |