JPS63313237A - Microcomputer - Google Patents

Abstract

PURPOSE:To rapidly response to an interruption request by storing interruption information with high using frequency in the 2nd storage device having a rapid access processing function so that the information is initially accessed at the time of generating an interruption. CONSTITUTION:A control circuit 3 receiving an interruption accepting signal S2 sends a vector information signal S3 to a detecting circuit 6. The circuit 6 detects the existence of branched information corresponding to a level included in the signal S3 in a cache memory 5. When the corresponding branched information exists, the control circuit 3 branches the signal S3 to a branched destination indicated in the branched information. When there is no corresponding branched information, the control circuit 3 inputs the branched information (i) stored in an external storage device 4 through a data bus DB, overwrites the information (i) in the cache memory 5 correspondingly to the i-th level and then branches the information (i) to a branched destination shown in the information (i).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer having an interrupt processing function that can perform interrupt processing at high speed.

(Conventional Pin*) FIG. 2 is a block diagram of a microcomputer having a conventional interrupt processing function. In the figure, an interrupt reception circuit 2 is provided in a microcomputer 1, and when an interrupt occurs, an interrupt request signal S1 is input to this interrupt reception circuit 2. This interrupt request signal S1 includes vector information, which is a series of numerical values for identification, corresponding to the interrupt factor. After the microcomputer 1 completes execution of the instruction currently being executed, the interrupt acceptance circuit 2
This interrupt request signal S1 is accepted, and the interrupt request signal S1
The interrupt acceptance signal S2 containing the vector information is sent to the control circuit 3 at the next stage.

Upon receiving this, the control circuit 3 saves the current internal state of the microcomputer 1 (program counter, program status register value, etc.) to a predetermined device of the external storage device 4. The external storage device 4 also stores, for each level indicated by the vector information, branch destination information of interrupt processing corresponding to that level.

After saving the internal state, the control circuit 3 accesses the i-th level storage device indicated by the vector information in the interrupt acceptance signal S2 on the external storage device 4, and stores the branch destination information 1 stored in the i-th level. Read via data bus DB,
Interrupt processing is performed by branching to the branch destination indicated by this branch destination information i.

[Problem that the invention seeks to solve]

As mentioned above, a conventional microcomputer with an interrupt processing function stores interrupt information such as branch destination information for interrupt processing in the external memory bag M every time an interrupt 8 occurs.
Interrupt processing was performed by reading from 4. Therefore, each time an interrupt occurs, a relatively long time is required to access the external storage device 4, which causes the problem that the throughput of this system decreases when executing an application system where interrupts occur frequently. there were.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a microcomputer having an interrupt processing function that can quickly respond to interrupt requests.

[Means for solving problems]

The microcomputer according to the present invention receives an interrupt request signal including vector information corresponding to an interrupt generation factor when an interrupt occurs, and in response to the interrupt request signal, a storage device corresponding to the vector information on a first storage device. In addition to the configuration in which interrupt information of the interrupt processing is obtained by accessing, a second storage device whose access processing is faster than the first storage device is provided, and on this second storage device, there is provided a second storage device that is frequently used. It stores interrupt information, determines whether or not corresponding interrupt information exists on the second storage device when an interrupt occurs, and if it exists, obtains the interrupt information and performs interrupt processing, and then determines whether the interrupt information exists. If not, the interrupt processing is performed by obtaining corresponding interrupt information from the first storage device.

(Function) The second device having a high-speed access processing function according to the present invention
The storage device stores frequently used interrupt information and is configured to be accessed first when an interrupt occurs, so most responses to interrupt requests are sent to the second storage device without accessing the first storage device. This can be done by accessing only the device.

(Embodiment) Fig. 1 is a block diagram showing the interrupt processing function of a microcomputer which is an embodiment of the present invention. Although the explanation will be omitted, the difference from the conventional model is that a cache memory 5 that can be accessed faster than the external storage bag H4 and a detection circuit 6 that detects branch destination information stored in the cache memory 5 are newly provided. Can be mentioned.

In the cache memory 5, branch destination information of frequently used interrupt processing is stored in advance in correspondence with the level of vector information, and the detection circuit 6 uses the vector information signal S3 given from the control circuit 3 to The presence or absence of branch destination information corresponding to the level indicated by the vector information is detected in the memory 5, and the detection result and the address value on the cache memory 5 to be accessed by the control circuit 3, which will be described in detail later, are detected. It is sent to the v4111 circuit 3 as a branch information detection signal S4. Note that db is an internal data bus provided between the cache memory 5 and the lllll circuit 3.

In such a configuration, when an interrupt occurs, an interrupt request signal S1 is input to the interrupt reception circuit 2. The interrupt acceptance circuit 2 accepts this interrupt request signal S1 after the microcomputer 1 executes the instruction currently being executed, and sends an interrupt acceptance signal S2 containing vector information to the next stage control circuit 3 as in the conventional art.

Upon receiving this, the tIIJwJ circuit 3 saves the current internal state of the microcomputer 1 and outputs the vector information signal S.
3 is sent to the detection circuit 6. The detection circuit 6 detects the presence or absence of branch destination information corresponding to the level included in the vector information signal S3 in the cache memory 5.

If the corresponding branch destination information exists in the cache memory 5, the storage address value (this is referred to as ADl) and information indicating the existence are included in the branch information detection signal S4, and t
Send to ilWJ circuit 3. Upon receiving this, the control circuit 3 reads the branch destination information stored at the address AD1 on the cache memory 5 via the data bus db, and executes the interrupt process by branching to the branch destination indicated by this branch destination information. be exposed.

On the other hand, if the corresponding branch destination information does not exist in the cache memory 5, information indicating the absence and L RU (
The address value of the branch destination information having the oldest access point (this is set as AC3) selected by the least recently used) method is included in the branch information detection signal S4 and sent to the control circuit 3.

Upon receiving this, the control circuit 3 accesses the i-th level storage device indicated by the vector information in the interrupt acceptance signal S2 from the external storage device N4, fetches the branch destination information i via the data bus db, and Interrupt processing is performed by associating destination information i with the i-th level and overriding address AD2 in the cache memory 5, and then branching to the branch destination indicated by branch destination information i.

In this way, by constantly storing frequently used branch destination information in the cache memory 5, responses to most interrupt requests are handled by the control circuit 3. This can be done in the dark using the cache memory 5 and the detection circuit 6. As a result, the external storage device 4 having a slow access time is rarely accessed, so the throughput of the microcomputer 1 hardly decreases even if interrupts occur frequently.

In this embodiment, the cache memory 5 is provided inside the microcomputer 1, but the present invention can also be implemented by providing an external second storage device with a fast access time. In addition, although only branch destination information is shown as interrupt information, information necessary for management in the operating system such as attribute values corresponding to interrupt factors may also be included, and interrupt requests are not limited to external interrupts.
The present invention can also be applied to internally generated interrupts.

Also, the RU method was shown as a replacement algorithm, but
FIFO method (first-in first-out
It is also possible to use other methods such as a first-in, first-out method, or to fix the branch destination information stored in the cache memory 5 without replacing it.

〔Effect of the invention〕

As explained above, according to the present invention, frequently used interrupt information is stored in a second storage device such as a cache memory having a high-speed access processing function, and when an interrupt occurs, the second storage device is first stored in the second storage device. Since the device is accessed, it is possible to obtain a microcomputer having an interrupt processing function that can quickly respond to an interrupt request.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the interrupt processing function of a microcomputer according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the interrupt processing function of a conventional microcomputer. In the figure, 1 is a microcomputer, 3 is a control circuit, 4 is an external storage device, 5 is a cache memory, and 6 is a detection circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) receiving an interrupt request signal including vector information corresponding to an interrupt generation factor when an interrupt occurs, and accessing a storage device corresponding to the vector information on a first storage device in response to the interrupt request signal; In a microcomputer that performs invitation processing by obtaining interrupt information for the interrupt processing, a second storage device whose access processing is faster than the first storage device is provided, and a frequency of use is stored on the second storage device. storing interrupt information with a high value, determining whether or not corresponding interrupt information exists on the second storage device when an interrupt occurs, and if so, obtaining the interrupt information and performing interrupt processing; If the microcomputer does not exist, the microcomputer performs interrupt processing by obtaining corresponding interrupt information from the first storage device. (2) the first storage device is provided externally;
The second storage device is provided internally.
The microcomputer described in Section 1.