JPH05100903A - Address tracer - Google Patents

Abstract

PURPOSE:To execute storage to a tracer memory in the case branch of a program is detected and branch is executed, in the address tracer for storing an outputted address, when a processor reads out an instruction from the memory. CONSTITUTION:The address tracer is provided with a register 5 for inputting an address and holding it temporarily, when a processor 2 reads out an instruction to be executed from a memory 1, a branch detecting circuit 6 in which the processor 2 compares an address of an instruction executed in the next time and the contents of the register 3 and detects whether branch exists or not, a tracer memory 9 for storing the address held in the register 3, in the case the break detecting circuit 6 detects the branch, a counter 8 for showing the address of the tracer memory 9, and a tracer control circuit 7 for executing write control, of the tracer memory 9 and updating the counter 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address tracer, and more particularly to a tracer memory capacity saving and trace time extending mechanism.

[0002]

2. Description of the Related Art Conventionally, in this type of address tracer,
The addresses of all the instructions executed by the processor were stored in the tracer memory in the order of execution.

[0003]

In the conventional address tracer described above, since the addresses of all the instructions executed by the processor are stored in the tracer memory in the order of execution,
In a short time, the memory capacity of the tracer becomes full,
There is a drawback that the trace time becomes very short.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address tracer which realizes saving of tracer memory capacity and extension of trace time.

[0005]

In order to achieve the above object, an address tracer according to the present invention is an information processing device comprising a memory and a processor for executing a program stored in the memory. The presence or absence of a branch by comparing the address of the next instruction with the register that takes in the address at which the instruction was stored and temporarily holds it when the processor reads the instruction from the memory A branch detection circuit that detects an address, a tracer memory that stores an address held in the register when the branch detection circuit detects a branch, a counter that indicates the address of the tracer memory, and a branch detection circuit that branches. Tracer control for writing the tracer memory and updating the counter when a Those having a road.

[0006]

When the instruction address output from the processor is fetched by the tracer memory, the branch is detected by the register and the branch detection circuit, and the address only when the branch is made is stored in the tracer memory.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, a memory 1 stores a program.

The processor 2 uses the address line 1 in the memory 1.
The instruction address is sent out by 1 and the program is received by the data line 10 and executed. Further, the processor 2 controls the writing and reading of the memory by the memory control signal 12
Is done by.

The address register 3 stores the instruction address as 1
It is fetched in byte units and held until the next instruction address is fetched.

The adder 4 calculates the instruction address to be executed in the next process from the instruction address received from the address register 3. The comparator 5 compares the fetched instruction address with the instruction address calculated by the adder 4, and communicates only when they do not match. Here, the adder 4 and the comparator 5 constitute a branch detection circuit 6.

The tracer control circuit 7 receives the memory control signal 12 when the comparator 5 communicates, and controls writing by the tracer memory control signal 14.

The tracer address counter 8 updates the counter indicating the address of the tracer. Reference numeral 15 is a tracer address line.

The tracer memory 9 stores the address of the tracer memory data line 13 and the tracer memory control signal 14.

Next, the operation of the present invention will be described. The processor 2 has an address line 11, a data line 10, and a control line 1.
The program stored in the memory 1 is read out and executed at any time in the order of execution via 2.

When the processor 2 reads an instruction from the memory 1, the address of the read instruction is stored in the address register 3.

When the processor 2 further reads the next instruction, the contents of the address register 3 are also updated to the address of the next read instruction.

As described above, the instruction read from the memory 1 by the processor 2 is stored in the address register 3 in 1-byte units at any time and held until the next instruction is read.

In the branch detection circuit 6, if there is no branch of the program from the contents of the address register 3, the 1-byte length instruction address fetched from the address register 3 is calculated by the adder 4 as the instruction address to be executed next. Then, the comparator 5 compares the instruction address with the address calculated by the adder 4, and notifies the tracer control circuit 7 of the presence / absence of a branch.

The tracer control circuit 7 monitors the notification of the presence or absence of a branch from the branch detection circuit 6 and, if there is no branch, does not write to the tracer memory 9.

When there is a branch, the address of the branch source stored in the address register 3 is written in the tracer memory 9, and the tracer address counter 8 indicating the address of the tracer is updated.

In this way, the branch detection circuit 6 monitors the presence or absence of a branch, and only when there is a branch, the tracer memory 9
Write control is performed.

[0024]

As described above, according to the present invention, when the instruction address output from the processor is fetched by the tracer memory, the branch is detected by the register and the branch detection circuit, and the tracer memory only detects the branch. Since the address is stored, there is an effect that the capacity of the tracer memory can be saved and the trace time can be extended.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 Memory 2 Processor 3 Address Register 4 Adder 5 Comparator 6 Branch Detection Circuit 7 Tracer Control Circuit 8 Tracer Address Counter 9 Tracer Memory 10 Data Line 11 Address Line 12 Memory Control Signal 13 Tracer Memory Data Line 14 Tracer Memory Control Signal 15 Tracer Address line

Claims (1)

[Claims] 1. An information processing apparatus comprising a memory and a processor for executing a program stored in the memory, wherein when the processor reads the instruction from the memory, the address at which the instruction is stored is set. A register for fetching and temporarily holding, a branch detection circuit for detecting the presence or absence of a branch by the processor comparing the address of the next instruction with the contents of the register, and the branch detection circuit if the branch detection circuit detects a branch A tracer memory that stores the address held in a register, a counter that indicates the address of the tracer memory, and a tracer control that performs write control of the tracer memory and update of the counter when the branch detection circuit detects a branch. An address tracer having a circuit.