JPS6146562A - Operation processing system of array element - Google Patents

Abstract

PURPOSE:To perform the operation processing of array data flexibly in a high speed by not only performing the operation of array elements but also obtaining the element number of an element corresponding to a specific value in array data of the operation result by one instruction. CONSTITUTION:The first and the second array element data to be subjected to vector operation are stored in vector operation data registers 3A and 3B, and their contents are operated, and the operation result is stored in a vector operation result register 5. If the operation result of the i-th element is set to the register 5 and contents of the register 5 coincide with those of a coincidence detecting register 6, contents of an element number counter 10 are transferred to an element number register 12 through an element number holding register 11. A coincidence detection mode flag 7 is set to ''0'', and contents of the flag 7 and the register 12 are checked to obtain the element number of the element corresponding to a specific value in the third array data also. Thus, the number of steps of a program is reduced, and the operation processing of array data is performed flexibly in a high speed.

Description

TECHNICAL FIELD The present invention relates to an arithmetic processing method for array elements, and more particularly to an arithmetic processing method for obtaining the element number of an element having a specific value in an array element for array data handled by an information processing device.

BACKGROUND ART Conventionally, in scientific and technical calculations, array data is often handled, and operations on this array data often involve repeating the same operations on each array element.

So-called vector instructions, which are specialized instructions for handling such array data at high speed, are used in conventional information processing devices.

Although the results of operations on array data are often used as is as separate array data, there are cases where it is necessary to perform special operation processing on array elements that correspond to specific values of the results of operations. In such a case, conventionally, all the results of this operation are once stored in the main memory using a normal vector instruction, and then the array data in the main memory is read out again using another instruction sequence to correspond to a specific value. The procedure is to check the array elements. Therefore, it has the disadvantage that high-speed processing is difficult.

Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks, and uses one instruction to not only calculate array elements, but also calculate the element number of the element corresponding to a specific value in the array data obtained as a result of this calculation. The purpose of the present invention is to provide a high-speed and flexible method for processing array data.

Composition of the Invention The arithmetic processing method according to the present invention performs arithmetic operations on first and second array elements in which each element is assigned an element number, and the result of this operation is converted into an element number in which each element is assigned an element number. In a vector operation such as storing in a third array element, a specific value register that can store the specific value in advance according to the element number of the element having a specific value in the third array element that is the result of the operation, and a specific value register specified by an instruction. A calculation means is used to perform calculations on the first and second array elements, and the content of the i-th element (1 is a positive integer) to be stored in the third array obtained from the calculation result and the specified storage means for storing the i-th element number when a match is detected by comparing the contents with the contents of a value register, and an element having a specific value in the third array element according to the storage contents of the storage means. The feature is that the element number of is calculated.

Example The present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a main storage device 1, a control unit 2, a vector operation data register 3
A and 381 bemo 4, vector operation result register 5, coincidence data register 6, coincidence detection mode flag 7, comparison circuit 8, AND (
It is composed of an AND) circuit 9, an element number counter 10, an element number holding register 11, and an element number register 12.

Programs and data are stored in the main memory device 1, and the contents are read out via a signal line 101, and data is written in via a signal line 102. The control unit 2 exchanges data with the main storage device 1,
It controls the operation of each circuit for decoding the read instruction word and executing various instructions including vector instruction accordingly.

The vector operation data registers 3A and 3B are registers that store data of the first and second array elements that are input to the vector operation, and the data is stored in the control unit 2.
is set via signal lines 103 and 104. The vector calculation circuit 4 includes the vector calculation data register 3A,
3B to signal 1105.1. The signal is received via Q6, and a predetermined vector operation is executed according to the instructions of the control signal sent from the control unit 2 via the signal line 107, and the operation result is sent via the signal line 108 to the vector operation result register 5. is stored in The contents of this vector operation result register 5 are transmitted to the control unit 2 via a signal line 109.
and finally written to the upper storage device 1 as data of the third array element.

The match data register 6 is a register that can be used to set appropriate data in advance using instructions other than vector instructions.
The data to be set is obtained via the signal line 110.

The coincidence detection mode flag 7 is a flip-flop that can be hit or reset by a signal line 111 from the control unit 2, and can be set in advance by a command.

Comparison circuit 8 receives the contents of vector operation result register 5 and match data register 6 via signal lines 112 and 113, and sets signal line 114 to be rIJ only when both data match as a result of the comparison. It is a circuit. The values of the signal line 114 and the output signal line 115 of the coincidence detection mode flag 7 are ANDed by the AND circuit 9.

The output of the AND circuit 9 is used to reset the match detection mote flag 7 via a signal line 116, and also issues an update instruction to the element number holding register 11 via a signal line 117.

The element number counter 10 receives an instruction from the control unit 2 via the signal line 118 at the start of vector calculation.
It is cleared to ``1'' every time the − element operation is executed.
Counts up by J. When the element number register 12 receives an update instruction via the signal line 119 from the control unit 2, the contents of the element number holding register 11 are transferred to the signal line 12.
The receiver is taken and stored through 0. Note that the contents of the match detection mode flag 7 and the element number register 12 are determined by the signal line 121.
．． 122 to the control unit 2, and can be used by other instructions or written to the main memory 2.

The processing operation for determining the element number of an element having a specific value in the new array data obtained as a result of the operation of the elements of the array data is shown in the flowchart of FIG. 2, and is performed in the following order.

The instruction word of the instruction to be executed read from the main memory device 1 is decoded by the control unit 2, and as a result, various control signals such as a request to read necessary data and designation of the type of operation are generated. The instruction to be executed now is a vector instruction for performing an operation on array data, and at the start of this vector instruction, the match detection mode flag 7 has already been set to "1" by the program, and the match data register 6 has already been set to "1". Assume that a specific value to be detected is set in .

The instruction word of the vector instruction to be executed is 4 words (-144
It has a length of ~) and has a format as shown in Figure 3. In FIG. 3, τOP is an operation code field that specifies the type of operation to be performed using the first array element or the second array element. yl is an address field for specifying the start address of the first array element, address modification specified by the MFI is applied to the value of yl, and the resulting value represents the element start address. ■2 and MF2 and y3 and M
F3 similarly determines the start addresses of the second and third array elements. VI+, VI2 and VT3 are the first. Second
and the third array, specify the difference in addresses between adjacent elements, that is, the distance between elements, and RN is the number of elements (
-n) specifies the register in which it is stored.

When this command is decoded by the control unit 2 and the leading elements of the first and second arrays are set in the vector operation data registers 3A and 3B, the vector arithmetic circuit 4 performs an operation according to the contents of the signal line 107. As a result, data to be stored in the main storage device 1 as the first element of the third array is obtained in the vector operation result register 5. Since the element number starts from rOJ, when the operation result of the first element is set in register 5, the element number counter 1
0 is cleared in rOJ, and thereafter each time the result of operation of a number of elements is set in the register 5, it is counted up by "1".

Now, suppose that the content stored in the register 5 as a result of the operation of the i-th element matches the content of the register 5, and the output of the AND circuit 9 becomes "1J", and at this time, the content of the element number counter 10 That is, ri-IJ is transferred to the element number holding register 11, and the match detection mode flag 7 is reset to rOJ. (+4-1
)-th and subsequent elements are not compared with the contents of register 6, and when the operation of the n-th element is completed, the contents of element number holding register 11 are the same as the one where a match was first detected. Element number ri-IJ corresponding to the element
is held. After the calculations for all n elements are completed, the content of the signal line 119 from the control unit 2 becomes [1]
Then, the contents of register 11 are transferred to element number register 12, and the vector instruction is completed. By checking the contents of the match mode detection flag 7 and the element number register 12, which are determined as a result of this vector instruction, the software program determines whether or not the desired specific data is detected in the third array data, and if a match is detected. You can know the element number of the element.

Effects of the Invention As explained above, the present invention has the ability to simultaneously obtain the element number of an element having a specific value in a new array element that is the result of an operation on an array element in a vector instruction that executes the operation. This makes it possible to reduce the number of steps in a program, which has the effect of speeding up processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device showing an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of a vector instruction executed in the device of FIG. 1, and FIG. FIG. 3 is a diagram showing the format of a command word for instructing a specific operation. Explanation of symbols of main parts 1...Main storage device 2...Control unit 3...Vector calculation data register 4...Vector calculation circuit 5... Vector operation result register 6...
・Coincidence register f...Coincidence detection mode flag 8...Comparison circuit

Claims (1)

[Claims] The first and second elements have element numbers assigned to each element.
In a vector operation in which an operation is performed on array elements and the result of this operation is stored in a third array element in which an element number is assigned to each element, a specific value in the third array element that is the result of the operation is An array element arithmetic processing method that calculates the element number of an element having a specific value register that can store the specific value in advance according to an instruction, and an operation that performs an operation on the first and second array elements specified by the instruction. and the contents of the i-th element (i is a positive integer) to be stored in the third array obtained by the operation result and the contents of the specific value register are compared, and when a match is detected, the a storage means for storing an i-th element number, and an arithmetic processing characterized in that the element number of an element having a specific value in the third array element is determined based on the storage contents of the storage means. method.