JPS63310054A - Bus arbitrating circuit - Google Patents

Abstract

PURPOSE:To prevent an occupation by a specific bus master by varying the phase of a clock signal CLK between a synchronizing flip-flop and a transmission flip-flop to allow each bus master to acquire a bus right sequentially. CONSTITUTION:1st logic circuits 12, 22, 23 are asserted by an input. Synchronizing FFs 13, 23, 33 assert an output signal in the timing of CLKs 1, 2, 3. Then the output of a 2nd logic circuit 14 is asserted and a bus acknowledge signal BACK 1 is outputted from a transmission FF. After the stop of request of a bus request signal BREQ1, 2nd logic circuits 24, 34 are asserted and when the BACK 2 is asserted, the logic circuit 34 is stopped. Then the stop of request of the bus request signal BREQ, the BACK 3 is asserted and the logic circuits 14, 34 are asserted and the BACK 3 is asserted. A 3rd BREQ 1 is asserted after the end of the BACK 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus arbitration circuit that adjusts the bus occupancy state when a plurality of bus masters share the bus. and improvements that are suitable for competing cases.

(Prior Art) The bus arbitration circuit has a method of prioritizing each bus master, which is known, for example, in Japanese Patent Laid-Open No. 58-149531 (Japanese Patent Application No. 57-31977) proposed by the present applicant. . In this way, when bus occupancy requests conflict, the bus occupancy is granted to the one with the highest priority, and the one with the lowest priority is placed on standby.

(Problem to be solved by the invention) However, in this method, if bus occupancy requests occur frequently, only those with high priority will use the bus, and those with low priority will occupy the bus less frequently. do. Therefore, there is a problem in that the bus usage efficiency of the system as a whole decreases.

The present invention solves these problems and aims to provide a bus arbitration circuit that grants bus use rights to each bus mask in a time-sharing manner.

(Means for Solving the Problems) A first invention that achieves the above object includes a plurality of bus request signal input sections and a bus approval signal output section provided one-to-one with these input sections. This bus arbitration circuit outputs a bus approval signal from any one output section when a plurality of bus request signals are present at the same time, and has the following configuration.

That is, a clock supply means is provided that generates a clock signal whose phase is sequentially shifted corresponding to the number of input/output channels.

Further, each input/output channel receives one of the bus request signals and a corresponding bus acknowledge signal, and outputs a bus request reception signal when the bus acknowledge signal is not output. A first logic circuit inputs this bus request reception signal and the bus request No. 18 and permits acceptance of the current bus request signal at the time when the bus approval signal has been reset for the previous bus request signal. A synchronized flip-flop samples the granted bus request signal with the corresponding clock signal sent from the clock supply means, to which all bus grant signals other than this channel are input, and the output signal of the bus grant signal is matched. a second logic circuit that outputs a bus request signal output from the synchronized flip-flop when
The present invention is characterized in that a transmission flip-flop is provided that samples the bus request signal output from the logic circuit using a clock signal supplied to an input/output channel adjacent in a certain direction and outputs the sample as a bus approval signal.

A second invention to achieve such an object is to input one of the bus request signals and a corresponding bus approval signal in place of the receiving flip-flop in the component of the first invention, and to receive the corresponding bus approval signal. A first gate circuit outputs a signal when no signal is output, and a bus request signal sampled by the gate circuit and a synchronized flip-flop or a bus grant signal transmitted from a transmission flip-flop is input, 7 is asserted, the second gate circuit supplies the bus request reception signal to the first logic circuit.

(Function) Each component of the present invention has the following function. The clock supply means sequentially supplies a phase-shifted clock signal to each input/output channel to provide information necessary for each input/output channel to sequentially output a bus acknowledge signal.

The receiving flip-flop and the first logic circuit accept the bus request signal only when the bus acknowledge signal is not output from the own channel. A synchronized flip-flop samples the bus request signal with its own channel's clock signal.

The second logic circuit allows output of the bus acknowledge signal only when no bus acknowledge signal is output from other channels. The transmitting flip-flop outputs the bus acknowledge signal at the timing of the adjacent channel, so the right to output the next bus acknowledge signal moves to the adjacent channel.

(Example of the first invention) The first invention will be described below with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of the first invention. In the figure, 10, 20, and 30 are input/output channels with one output per person, and each bus request signal @ B R
Input E Q 1, 2.3 and bus acknowledge signal BACK
1, 2.3 are output. 40 is a clock supply means for generating a clock signal whose phase has changed sequentially corresponding to the number of input/output channels;
The check signal CLK is 1, 2.3.

Next, configure each input/output channel as input/output channel 1.
0 will be explained as a representative example, and the other input/output channels will be given corresponding numbers and the explanation will be omitted. 11 inputs the bus request signal BREQI and receives the bus acknowledge signal BACK1.
is the input of the reset terminal of the receiving flip-flop,
If the bus acknowledgment signal BACK1 is not output, a bus request reception signal is output. 12 is the bus request signal BRE
A first logic circuit that ANDs Q1 and the bus request reception signal allows the current bus request signal BREQI to be accepted until the reset of the bus acknowledge signal BACK1 in response to the previous bus request signal BREQ1 is completed. Reference numeral 13 denotes a synchronized flip-flop which samples the bus request signal BREQ1, which has been granted by the first logic circuit 12, with the output clock signal CLK1, and which receives the initialization signal INZ at its reset terminal. . 14 is a second logic circuit which inputs and ANDs the bus acknowledge signal 8ACK2゜3 of the input/output channel 20.30 and the bus request signal BREQ1 output from the synchronization flip 7O block 13; The bus request signal BREQ1 is output only when BACK2.3 is present. 15 samples the bus request signal BREQ1 output from the second logic circuit 14 and generates the bus acknowledge signal BAK.
1, the clock signal CLK2 for the adjacent input/output channel 20 supplied by the clock supply means 40 is used as a timing signal, and the initialization signal NZ is input to the reset terminal. has been done. Note that the bus acknowledge signal BACK 2.3 input to the second logic circuit 14 is the bus acknowledge signal BACK output from the transmission flip-flop 25.35 due to logic reasons.
The signal is complementary to 2.3.

The operation of the device configured in this manner will be described next. Second
The figure is a waveform diagram of the apparatus of FIG. 1. Here, the initialization signal INZ is first supplied, and then the bus request signal BRE is supplied.
Let us explain the case where three Q1, 2.3 conflict at the same time as an example. The clock signals @CL K 1, 2.3 have a period TIT as shown, and each signal has a rising pulse with a phase difference of T/3.

In the figure, the bus request signal B RE Q 1, 2.3 is 3.
It is simultaneously input to each input/output channel 10, 20, and 30.

Then, since the bus acknowledge signal BACK 1.2.3 is not output from any of the input/output channels 10, 20.30, the output signal of the first logic circuit 12, 22.32 is asserted. be done. In (2), each synchronization flip-flop 13, 23.33 asserts output No. 3 seven times at the timing of the clock signal CL K 1, 2.3 supplied thereto. At (2), the output signal of the second logic circuit 14 is asserted, and then at (2), the bus acknowledge signal BACKI is output from the transmission flip-flop 15. Since the bus acknowledge signal BACK1 is output,
The output signal of the second logic circuit 24.34 is negated (ne
gate).

Next, when the request of the bus request signal BREQI is stopped, the output signal of the synchronization flip-flop 13 is completely raised at the timing of the clock signal CLK1, and following this, the bus acknowledge signal @ B A CK 1 is raised to the clock signal CLK2.
is rounded up slightly later. Then, at ■, the output signal of the second logic circuit 24.34 is asserted, and then at ■, the bus acknowledge signal BA is asserted at the timing of clock signal CLK3.
CK2 is asserted. This causes the output signal of the second logic circuit 34 to be rounded up again.

Next, when the request of the bus request signal BREQ2 is stopped, the output signal of the synchronization flip-flop 23 is rounded up at the timing of the clock signal CLK2, and following this, the bus grant signal BAcK2 is slightly lower than the clock signal C:LK3. Rounded up late. Therefore, the second logic circuit 14.
The output signal No. 34 is asserted, and then the bus acknowledge signal BACK3 is asserted at the timing of the clock signal CLK1 at (2). Note that the output signal of the second logic circuit 14 is asserted here because of the first bus request signal @BR
This is in response to the fact that the second bus request signal BREQ1 was issued after EQ1 was acknowledged.

However, the second bus request signal BREQ1 is canceled before the bus approval signal BREQ1 is acknowledged.

Next, when there is a third bus request signal BREQ1 at (2), the corresponding bus request signal BREQ1 is asserted at [stock] with the rounding up of the bus acknowledge signal BACK3. In the figure, the fourth bus request signal BREQ1 is subsequently requested, and the same operation as the third one is performed.

It should be noted that the length of the asserted portion (H) of the pulse width of each bus request signal B RE Q 1, 2.3 is longer than the period T of the clock signal CLK, and the length of the negated portion 1) is longer than the period T of the clock signal CLK. This is longer than the sum of the delay time of the second logic circuit 14, the reset release time of the receiving flip-flop 11, and the set pulse width. - FIG. 3 is a configuration block diagram of a modified embodiment of the first invention. In FIG. 1, the synchronizing flip-flop 12.23.3
3 and transmission flip-flops 15, 25, and 35, D-type flip-flops with reset are used.
The synchronization flip-flops 12, 23.33 and the transmission flip-flops 15, 25.35 shown in the figure are simple flip-flops.

Therefore, in order to smooth the initialization operation, the first logic circuit 12, 22.
I'm using human power AND.

(Embodiment of the second invention) FIG. 4 is a configuration block diagram showing an embodiment of the second invention,
Only one channel out of multiple input/output channels is shown. This invention realizes the reception flip-flop 11 in the first invention using a gate circuit, and can be easily applied to a custom IC using a gate array. In FIG. 4, parts having the same functions as those in FIG.

In the figure, 111 is an AND gate circuit which receives the bus request signal BREQ1 and the bus acknowledge signal BACK1 as input.
The bus request signal BREQ1 is output only when the bus acknowledge signal BACK1 is not output. 112 is AND
It is an OR gate circuit which receives the output signal of the gate circuit 111 and the feedback signal as input, and if either one is asserted, it supplies the bus request signal BREQ1 to the first logic circuit 12. This period signal may be the bus request signal BRQ1 sampled by the synchronization flip-flop 13 as shown, or may be the bus acknowledge signal BACK1 transmitted from the transmission flip-flop 15.

In such a device, the AND gate circuit 111 serves to round up the bus request signal BREQ1 by sending out the bus acknowledge signal BACK1, and the OR gate circuit 112, once it receives the bus request signal BREQI, holds it in the synchronization flip-flop 13. playing a role.

(Effect of the invention) As explained above, the present invention has the following effects.

(1) Since the phase of the clock signal CLK is changed between the IfSJ synchronization flip-flop and the transmission flip-flop, each bus master can sequentially obtain bus rights, and only a specific bus master can use the bus. It is possible to prevent a situation where the company has a monopoly on the

(2) It is known that a metastable state occurs when the D input and T input of a flip-flop conflict. Since the phase of CLK is changed by an appropriate value, metastability can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an embodiment of the first invention, FIG. 2 is a waveform diagram of the device shown in FIG. 1, and FIG. 3 is a configuration block diagram of a modified example of the first invention. , FIG. 4 is a configuration block diagram showing an embodiment of the second invention. 10.20.30...Input/output channel, 11,21
．． 31...Reception flip-flop, 12, 22.32
...First logic circuit, 13.23.33--Synchronization flip-flop, 14,24,34°° Second logic circuit, 15,25.35--Transmission flip-flop,
111, 112...Gate circuit.

Claims (2)

[Claims] (1) An input section for a plurality of bus request signals, and an output section for a bus approval signal provided one-to-one with these input sections, and when there are multiple bus request signals at the same time, bus approval is sent from any one of the output sections. In the bus arbitration circuit that outputs the signal, a clock supply means is provided for generating a clock signal whose phase has shifted sequentially corresponding to the number of input/output channels, and one of the bus request signals and a bus approval signal corresponding thereto are input. and a reception flip-flop that outputs a bus request reception signal when the bus acknowledgment signal is not output; a first logic circuit that allows acceptance of the current bus request signal after the completion of the bus request; a synchronized flip-flop that samples the bus request signal allowed by this logic circuit with a corresponding clock signal sent from the clock supply means; All bus acknowledge signals other than this channel are input,
a second logic circuit that outputs the bus request signal output from the synchronized flip-flop when the output signal of the bus acknowledge signal is open; a second logic circuit that outputs the bus request signal output from the logic circuit; A bus arbitration circuit characterized in that each input/output channel is provided with a transmission flip-flop that samples a clock signal supplied to the channel and outputs it as a bus approval signal. (2) An input section for a plurality of bus request signals, and an output section for a bus approval signal provided one-to-one with these input sections, and when there are multiple bus request signals at the same time, bus approval is sent from any one output section. In the bus arbitration circuit that outputs the signal, a clock supply means is provided for generating a clock signal whose phase has shifted sequentially corresponding to the number of input/output channels, and one of the bus request signals and a bus approval signal corresponding thereto are input. and a first gate circuit that outputs a signal when the bus approval signal is not output; the output signal of this gate circuit and the feedback signal are input; if either one is asserted, a bus request reception signal is output; a second gate circuit that outputs the bus request signal; a logic circuit, a synchronized flip-flop for sampling the bus request signal granted by this logic circuit with a corresponding clock signal sent from the clock supply means, to which all bus grant signals other than this channel are input;
a second logic circuit that outputs the bus request signal output from the synchronized flip-flop when the output signal of the bus acknowledge signal is open; a second logic circuit that outputs the bus request signal output from the logic circuit; A transmission flip-flop that samples the clock signal supplied to the channel and outputs it as a bus acknowledge signal is provided in each input/output channel, and the feedback signal is the bus request signal sampled by the synchronization flip-flop or the transmission flip-flop. A bus arbitration circuit characterized in that the bus approval signal is transmitted from a bus arbitration circuit.