JPH06103230A - System/bus arbitration circuit device - Google Patents

Abstract

PURPOSE:To make it possible to simply increase and connect data processors to a competition arbitration circuit in a data processor system without changing the circuit. CONSTITUTION:This system bus arbitration circuit device characterized by consisting of a competition arbitrating circuit 1 for arbitrating the use of a system bus in the data processor system, plural data processors 2a, 2b for asynchronously requesting the use of the system bus and a system bus arbitrating circuit 3 arranged on a using request signal R2 line and a use permitting signal S2 line connected between the circuit 1 and the processors 2a, 2b so as to select a system bus using request with the maximum priority out of plural system bus using requests outputted from the plural data processors and generate the permission of use to the data processor generating the using request with the maximum priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a competitive arbitration circuit device which is arranged in a data processing system such as a computer and arbitrates competition for use with a system bus or the like.

[0002]

2. Description of the Related Art Generally, in a data processing system such as a computer, a system in which a plurality of data processing devices such as a processor and a peripheral control device use a system bus or a shared resource in a system such as a main memory device in a time division multiplex is adopted. Has been done.

In such a data processing system, in order to facilitate the use of the shared resource in the system by each data processing device, a competitive arbitration circuit for centralized management is provided in the system, and each data processing device has this contention arbitration. A method of issuing a use request to a circuit in advance and starting to use the shared resource after receiving the use permission is adopted. In such a competitive arbitration circuit, when the usage requests from the respective data processing devices compete with each other, how to arbitrate them becomes an important issue for enhancing the processing capability of the entire system.

The simplest form of contention arbitration is to register usage requests in a queue in the order of occurrence and to grant usage permission in the order of registration.

As another typical example of the contention arbitration method, from the viewpoint of the processing capacity of the entire system, a fixed use priority is given to each data processing device, and use requests from data processing devices having different priorities are given. If there is a conflict, there is a permission to use the highest priority data processing device.

As still another typical example of the contention arbitration method, the priority given to each data processing device is not fixed,
Some change dynamically according to the usage status of the shared resources. For example, when a plurality of usage requests compete with each other, the usage permission is given according to a predetermined priority order at first, but the usage permission is given to the newest one at a lower priority, and the usage request is cyclically given to each usage request. It is a method of giving permission to use.

Further, as another typical example of the contention arbitration method, all the usage requests from the respective data processing devices are temporarily sent in synchronization with the acceptance permission, regardless of the unique priority. After the acceptance, there is a method of granting the usage permission to the highest priority data processing device according to the unique priority.

[0008]

None of the conventional competitive arbitration circuits described above solves the problems of the prior art described below. That is, conventionally, the use request signal of the competitive arbitration circuit is unique to the hardware,
Since the system is predetermined, there is a limitation that the system can connect only a data processing device for a predetermined use request signal, and the data processing device side is also designed according to the competitive arbitration circuit. Therefore, when it is desired to add more data processing devices than the limited number, there is a problem that it is necessary to add a circuit to the contention arbitration circuit side.

Therefore, it is an object of the present invention to increase the number of data processing devices connected to a competitive arbitration circuit of a data processing device system to undergo arbitration by increasing the number of connected arbitration circuits or more without increasing the number of circuits of the competitive arbitration circuit. It is to increase the versatility of the number of data processing devices that can be connected to the contention arbitration circuit by making it possible to easily add more.

[0010]

In order to solve the above problems, the present invention asynchronously requests the use of the system bus and a contention arbitration circuit that arbitrates the use of the system bus in a data processing system. A plurality of data processing devices, arranged on the use request signal line and the use permission signal line connected between the contention arbitration circuit and the plurality of data processing devices, and of the system bus from the plurality of data processing devices. A system bus arbitration circuit for selecting the highest priority use request and issuing a use permission to the data processing device that has issued the highest priority use request. is there.

In order to solve the above problems, the present invention provides a contention arbitration circuit that arbitrates the use of a system bus in a data processor system and a plurality of data processors that asynchronously request the use of the system bus. A system bus arbitration circuit arranged on a use request signal line and a use permission signal line to be connected, and selects one of the highest priority among use requests of a plurality of system buses issued from the data processing device. A priority logic unit, a use permission register unit that latches and holds a use request signal of the highest priority selected by the priority logic unit with a use permission signal from the contention arbitration circuit, and a predetermined time from the reception of the use permission signal. It further comprises a use permission signal generating section for issuing a use permission signal to the data processing device which has issued the use request signal.

[0012]

According to the present invention, a plurality of data processing devices can be connected to each of the use request signal and the use permission signal of the contention arbitration circuit of the data processing device system, and the plurality of data processing devices can be connected. Arbitration of bus competition can be easily realized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. This embodiment will be described as an example in which the present invention is applied to the above-mentioned prior art, Japanese Patent Laid-Open No. 3-171362. Of course, the present invention is not limited to the application of this embodiment. First, the overall configuration of the system bus contention arbitration circuit device in a data processing system according to an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing the overall configuration of a system bus contention arbitration circuit device. Reference numeral 1 is a use request signal and a use permission signal (R1 _, R) to a data processing device.
2 and S1 _, S2) each having two ports, and a arbitration arbitration circuit of the data processor system for arbitrating a use request of the system bus by the data processor, 2a and 2b are indirectly, and 2c is a direct arbitration. System for circuit 1
A data processing device 3, which issues a bus use request, is connected between the plurality of data processing devices 2a and 2b and the contention arbitration circuit 1, and issues a bus use request from the data processing device to the contention arbitration circuit to the contention arbitration circuit. , A system bus arbitration circuit that issues a use permission from a contention arbitration circuit to a data processing device that issues a use request of the highest priority.

The competitive arbitration circuit 1 is of the prior art,
Data processing device 2 via system bus arbitration circuit 3
bus use request issued from a and 2b and data processing device 2c
It arbitrates the bus use request issued directly from the device and issues the bus use permission to the higher priority, but the system bus arbitration circuit 3 arbitrates which of the data processing devices the bus use permission received is further applied. To do.

In this embodiment, two data processing devices are connected to the contention arbitration circuit via the system bus arbitration circuit 3, and another data processing device 2c is directly connected to the contention arbitration circuit 1. However, any number of system bus arbitration circuits 3 may be connected as long as they are within the limited number of ports of the use request signal and the use permission signal of the contention arbitration circuit 1. Any number of data processing devices may be connected, and the configuration is arbitrary.

FIG. 2 is a circuit configuration diagram showing the system bus arbitration circuit 3 in detail. In FIG. 2, 5, 7, 14 are AND gates, 6, 8, 9, 15 are inverters, 10
a and 10b are flip-flops, 11a and 11b are output gates, 12 is an OR gate, 13 is a delay element, and R2
_, ra , Rb are use request signals, and S2 _, sa _, sb are use permission signals.

The configuration of the system bus arbitration circuit 3 will be described in detail below with reference to FIG. The system shown in Figure 2
The bus arbitration circuit 3 receives the system bus use request signals ra and rb from the data processors 2a and 2b, and determines the order of priority together with the inverters 6, 8 and 9 (used in this embodiment, the AND gates 5 and 7). Request signal ra has a higher priority), and
Use permission register section having flip-flops 10a, 10b which receive the output signals ra ^' , rb ^' of the gates 5, 7 at their logic inputs and latch them via the inverter 15 by the use permission signal S2 from the contention arbitration circuit 1. Including and

Further, the system bus arbitration circuit 3 includes a delay element 13 for delaying the use permission signal S2 sent from the contention arbitration circuit 1 of the data processing system by a predetermined time,
Use permission signal S2 AND gate 14 which ANDs the output signal of the delay element 13 and the use received from the outputs of the flip-flops 10a and 10b for the data processing devices 2a and 2b in synchronization with the output signal of the AND gate 14. Output gates 11a _, 11 for sending the permission signals sa _, sb
and a data processing device 2 and
The OR gate 12 sends the use request signal R2 to the contention arbitration circuit 1 of the data processing system by taking the logical sum of the use request signals issued from a and 2b.

Next, referring to FIG. 2 in addition to the timing diagram of FIG.
The operation of the system bus arbitration circuit 3 according to the embodiment of the present invention shown in FIG. Two data processing devices 2
The use request signals ra and rb, which are asynchronously issued from a and 2b, respectively, are supplied to the system bus arbitration circuit 3.

It is now assumed that the two use request signals ra and rb are both off and both outputs r1 and r2 of the flip-flops 10a and 10b are off. In this state, the use request signal ra or rb is the AND gate 5
Or, when it is input to one of the inputs, its output ra ^'
Or rb ^' is input to the logic input of the flip-flop 10a or 10b and inverted, and its output r1 Or r2 Turn on. Flip-flop 10a or 1
0b is the use permission signal S2 input thereafter, as described later. On its rising edge, its on-state is latched.
On the other hand, the use request signal ra or rb is OR'ed by the OR gate 12 and is output to the competitive arbitration circuit 1 as the use request signal R2. Wait for the output of the signal S2.

Now, assuming that the use request signals ra and rb are simultaneously input to the AND gates 5 and 7, the use request signal ra is input to one input of the AND gate 5,
The other input of the AND gate 5 is ON since the output of the inverter 6 is ON because the output rb of the flip-flop 10b is OFF according to the above assumption. Therefore, the output ra ^' of the AND gate 5 is turned on and input to the logic input of the flip-flop 10a.

At the same time, the use request signal ra is sent to the inverter 9
To the other input of the AND gate 7, the use request signal rb
AND gate 7 even if input to one input of gate 7
Is not opened and its output rb is not turned on. Therefore, the flip-flop 10b does not operate and the use request signal ra Wait until is turned off. That is, the use request signal ra has higher priority than rb.

That is, in FIG. 3, the use request signal r
When a and rb rise at the same time, the output r2 of the flip-flop 10b is off, and the AND gate 5
Flip at the output ra ^'whereas almost rises at the same time request signal ra rises, the AND gate 7 outputs ^rb' is the request signal ra off and rb on state
It shows that the output r1 of the flop 10a waits until it is turned off, and then rises on at the falling edge of the output r1.
Further, the usage request signal R2 for the contention arbitration circuit 1 is kept on while either of the usage request signals ra and rb from the data processing devices 2a _and 2b is on, and the usage permission signal S2 from the contention arbitration circuit 1 is maintained. Wait for

The flip-flop 10a is turned on by the output ra 'of the AND gate 5 and its output r1 is turned on immediately, but as shown by the dotted line in FIG. 3 by the use permission signal S2 from the contention arbitration circuit 1. Is completely latched, and is kept in the ON state until the use permission signal S2 is turned off even if the use permission signal ra is turned off. The output r2 of the flip-flop 10b is turned on when the use request signal ra is off and the output r1 of the flip-flop 10a is off because the use request signal rb is still on.

The output r2 of the flip-flop 10b is
After that, when the use permission signal S2 is turned on, it is completely latched by the rising edge thereof as shown by the dotted line in FIG. 3, and then the use request signal ra rises again, and the output rb ′ of the AND gate 7 rises. Even if it is turned off, it is not turned off until the use permission signal S2 is turned off, and the latched data is held. Also, the output r of the flip-flop 10b
Even if the use request signal ra is turned on again while 2 is on, the output ra 'of the AND gate 5 does not turn on until the output r2 is turned off, and turns on again when the output r2 turns off. The above operation is repeated.

On the other hand, the contention arbitration circuit 1 outputs the use permission signal S.
When 2 is input, the delay signal Sd delayed by the delay element 13 is input to one input of the AND gate 14.
Since the use permission signal S2 has already been input to the other input of the AND gate 14, the enable signal Soe is output from the output of the AND gate 14. The enable signal Soe enables the output gates 11a _and 11b, but when the output r1 of the flip-flop 10a is on, the output gate 11a gates it and outputs the use permission signal sa to the data processing device 2a. , The output gate 11 when the output r2 of the flip-flop 10b is on.
b gates it and outputs the use permission signal sb to the data processing device 2b.

Now, the data processing device 2a uses the use permission signal s.
When a is received, in order to reset the use request signal ra, as described above, the output ra 'of the AND gate 5 is turned off, the bus processing is performed, and after that, the contention arbitration circuit 1 outputs the use permission signal S2. When the sending is stopped, the latch of the flip-flop 10a is released, and at that time,
Since the output ra 'of the gate 5 is also off, the output r1 of the flip-flop 10a is turned off. Then, as described above, the AND gate 7 is opened to turn on its output rb 'and turn on the output r2 of the flip-flop 10b. The output r2 is the output gate 11 enabled by the enable signal Soe generated as described above.
The use permission signal sb is transmitted to the data processing device 2b via b. The data processing device 2b resets the use request signal rb and performs bus processing, and as a result turns off the output rb 'of the AND gate 7. When the bus processing is completed, the contention arbitration circuit 1 turns off the use permission signal S2, the latch of the flip-flop 10b is released, and the output rb 'of the AND gate 7 is also off. The output r2 is also turned off, and the use permission signal sb is turned off via the output gate 11b.

Next, a case where the data processing device 2a outputs the next use request signal ra while the data processing device 2b is using the bus will be described. In this state, when the use request signal ra turns on, it turns off the output rb ′ of the AND gate 7 via the inverter 9, but since the use permission signal S2 is still on, it causes the flip-flop 10b to turn on. Latch in the on state and its output is on, which closes AND gate 5 and its output ra '
Is maintained in the off state, and waits for the use permission signal S2 to be turned off upon completion of the bus processing of the data processing device 2b. When the data processing device 2b receives the use permission signal sb, it turns off the use request signal rb, but since the output rb 'of the AND gate 7 is already in the off state as described above, it has no effect.

When the bus processing by the data processor 2b is completed, the contention arbitration circuit 1 of the system causes the use permission signal S2.
Is reset, the latch of the flip-flop 10b is released and its output r2 is turned off. This turns on the two inputs of AND gate 5,
The AND gate 5 opens and its output ra 'turns on, turning on the output r1 of the flip-flop 10a. Then, as described above, the use permission signal sa is sent from the output gate 11a to the data processing device 2a.

[0031]

As is apparent from the above description, according to the present invention, by adding the system bus arbitration circuit to the use request signal line and the use permission signal line for the contention arbitration circuit of the data processor system, It has become possible to easily increase or change the number of data processing devices to be connected without increasing or changing the contention arbitration circuit and without imposing a load on the bus.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a contention arbitration circuit device of a data processing device system according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a circuit configuration of a system bus arbitration circuit of FIG.

FIG. 3 is a timing diagram for explaining the operation of the system bus arbitration circuit of FIG.

[Explanation of symbols]

1 Competitive Arbitration Circuit 2a to 2c Data Processor 3 System Bus Arbitration Circuit 5, 7, 14 AND Gate 6, 8, 9, 15 Inverter 10a , 10b Flip-flop 11a , 11b Output gate 12 OR gate 13 Delay element R1 _, R2 _, ra _, rb Usage request signal S1 _, S2 _, sa _, sb Usage permission signal

Claims (2)

[Claims] 1. A contention arbitration circuit for arbitrating the use of a system bus in a data processor system, a plurality of data processors requesting the use of the system bus, the contention arbitration circuit and the plurality of data processors. Is arranged on the use request signal line and the use permission signal line connected between the two, and selects the highest priority one of the system bus use requests from the plurality of data processing devices. A system bus arbitration circuit device comprising: a system bus arbitration circuit configured to issue a usage permission to a data processing device that has issued a usage request. 2. A use request signal line and a use permission signal for connecting a competitive arbitration circuit for arbitrating the use of a system bus in a data processing device system and a plurality of data processing devices for asynchronously requesting the use of the system bus. A system bus arbitration circuit arranged on a line, the priority logic unit selecting one of the highest priority among the plurality of system bus use requests issued from the data processing device; A usage permission register unit that latches and holds a selected usage request signal of the highest priority with a usage permission signal from the contention arbitration circuit, and data processing that issued the usage request signal after a predetermined time from the reception of the usage permission signal. A system bus arbitration circuit comprising: a use permission signal generation unit that issues a use permission signal to a device.