JPH0384651A - Dma transfer control system - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the DMA transfer speed of a higher rank bus master by detecting the conflict with the higher rank bus master via a lower rank bus master and increasing an output cycle to give the preference to the DMA transfer of the higher rank bus master. CONSTITUTION:A cycle control means 19 of a lower rank bus master 30b increases the output cycle of its own bus using request if a higher rank bus master 30a outputs a bus request at output of the bus using request. Thus the master 30a first acquires a bus at conflict and then the master 30b acquires the bus. However the bus output request of the master 30b is delayed. Therefore the master 30a can acquire continuously the bus. Thus the DMA transfer speed is increased at the higher rank side.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a DMA transfer control system, and in the Imozuru bus arbitration system that acquires a common bus for each transfer unit and performs DMA transfer, when multiple bus masters simultaneously perform DMA transfer, The purpose of this module is to improve the reduction in DMA transfer speed of the upper-level bus master, by outputting a bus request signal at a fixed cycle to the connected bus request line, and acquiring the right to use the bus with priority over the connected upper-level side. In a data processing device equipped with a plurality of bus masters that transfer data by DMA, a lower bus master is provided with cycle control means for extending the output cycle of its own bus use request signal when it competes with a bus use request signal of an upper bus master, The configuration is such that the lower bus master detects a conflict with the higher bus master, extends the output cycle, and gives priority to the DMA transfer of the higher bus master.

[Industrial application field]

The present invention relates to improvements in DMA transfer control methods.

2. Description of the Related Art As data processing devices become more sophisticated and faster, devices in which a plurality of bus masters share a common bus are becoming popular.

As exclusive control performed when this bus master monopolizes the common bus, bus use request signal lines (hereinafter referred to as bus request lines) are connected between each bus master, and bus use requests from each bus master are generated simultaneously (11 cases). In this case, a bus arbitration method is often adopted in which the bus master on the upper connection side of the bus request line (hereinafter referred to as the upper bus master) acquires the right to use the bus preferentially.

In this Imozuru bus arbitration method, in DMA transfer, transfer control is performed in which a series of data is transferred by outputting a bus use request for each transfer unit at a fixed cycle, but when multiple bus masters perform DMA transfer at the same time. When individual requests to use the bus compete, the higher-level side acquires the bus preferentially, but in the end, DMA transfer is performed in a time-sharing manner according to the cycle, which significantly reduces the DMA transfer speed of the higher-level side. There are challenges.

Therefore, there is a need for a DMA transfer control method that increases the DMA transfer speed on the upper side when DMA transfers are performed in parallel.

[Conventional technology]

FIG. 4 is an explanatory diagram of the Imozuru type bus arbitration system, FIG. 5 is a time chart when there is no contention, FIG. 6 is a time chart when there is contention, and FIG. 7 is a block diagram of a conventional bus control unit.

In FIG. 4, a plurality of bus masters 30a (upper side of the continuous connection) and 30b (lower side) are each equipped with a bus control unit, and when a DMA request occurs, they output a bus use request signal to the bus request line 20. (Please read this BRQO)
do.

The bus masters 30a and 30b are connected by this bus request line 20 via AND circuits 9a and 9b, and the bus use request signal *BRQO outputted from each bus master 30a and 30b (however, when viewed from the lower side 30b, the upper The signal R on the side 30a (to is the real BRQi) is ORed by AND circuits 9a and 9b and received by the bus arbiter 31.

When the bus request line 20 goes low, the bus arbiter 31 outputs a bus permission signal to the bus permission line 2I (*BACK
L').

As a result, each bus master 30a, 30b receives this bus permission signal (auxiliary ACK) if the higher-order side has not outputted the bus use request signal (*BRQi), and if it has outputted it, it receives the bus request signal (main). It waits for the next bus permission signal (to this BAC) while outputting BRQO).

In this way, the higher-order bus master 30 is always connected
The bus usage request of a is accepted with priority.

FIG. 7 shows a bus control section that outputs bus use requests at regular intervals and performs DMA transfer.

When a DMA request is output via the flip-flop FF 14, the period data stored in the period setting register 11 is loaded into the period counter 12, and the count is enabled (EN ON), so that the period counter 12 starts clocking. Start counting, and after counting a predetermined number, carry RC
Output.

Based on this RC output, if the DMA request continues (Q terminal of FF 14 is 11"), cycle data is loaded from the cycle setting register 11 into the cycle counter 12 again.
RC is output again.

This operation is repeated until the DMA transfer is completed and the FF 14 is reset.

The RC output at regular intervals in this manner serves as an output instruction signal for the bus use request signal *BRQO.

This output instruction signal is temporarily held in JKFF 17,
The AND circuit 13 causes the bus permission signal (*BAC
A signal indicating whether or not K) has been acquired (Book BG) (JK
When the q terminal output of FF 6 is 11', it is output to JKFF 1.

In other words, even if the right to use the bus is acquired, output of the next bus request is prohibited before data transfer starts.

When the J terminal of JKFF 1 becomes H”, JKFF 1
The ear terminal becomes L', the bus request line 20 is tied to "L", and a bus use request signal is output (NeBR port 0 is "L").
do.

This JKFF I has a bus permission signal *BACK of L゛(
bus permission) and BRQi is .degree.11 (the higher-order side has not outputted a bus use request), that is, when it has acquired the right to use the bus.

At this time, the JKFF 6 holds the output of the AND circuit 4, sets the Q terminal to L°, and notifies the DMA request destination of acquisition of the right to use the bus.

In this state, the common bus is opened (*B of control line 23
BSY is It') and JKFF 9. The main BBSY of the control line 23 is set to L' via the inverter 10, DMA transfer is started, and the reception response (main R
DY is "H"), the main BBSY is set to °H' and the common bus 32 is opened.

The above operation of the bus control unit is explained in the fifth section for the case of no contention.
Shown in the figure.

In this figure, the constant period TI output from the period counter 12
A bus use request signal (this BIl
iQO) is output, each time a bus is acquired and DMA
It is indicated that the transfer will take place.

FIG. 6 shows a time chart in the case where there is a conflict with the DMA transfer of the higher-order bus master 30a and a bus usage request, and shows a case where the higher-order side is set faster than the lower-order side.

According to this figure, when bus use request signals are output at the same time (main BRQO and umbrella BRQ i are both “L”), the higher-order side acquires the bus first, but the lower-order side outputs the bus use request signal (main BRQO and umbrella BRQ i are both “L”). Mouth 0 remains L′), and book BG]
When it becomes 1', the next bus permission (*BACK is L') is output from the arbiter 31, so the lower side acquires the lotus next.

Similarly, a bus use request is output based on the carry RC output from each cycle counter 12, and the cycle! tlI
T1. 32 common lotuses are acquired at a rate according to T2,
DMA transfer between the upper and lower sides is performed on a time-sharing basis.

[Problems to be Solved by the Invention] In the conventional method described above, when a series of data is transferred by DMA by outputting a bus usage request at a fixed cycle for each transfer unit, if the lower side performs DMA transfer in parallel. , there is a problem that the DMA transfer speed on the upper side becomes significantly slow.

For this reason, it is better to set the lower cycle later, but
When DMA transfer is performed independently, a problem arises in that the transfer speed on the lower side is slow.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a DMA transfer control method that improves the reduction in DMA transfer speed on the upper side when DMA transfers are performed in parallel.

[Means for Solving the Problems] In order to achieve the above object, the DMA transfer control system of the present invention provides a bus request line 2 as shown in FIG.
The lower bus master 30b is provided with a cycle control means 19 for extending the output cycle of its own bus use request signal when it competes with the bus use request signal of the higher bus master 30a which is always connected in series with the lower bus master 30b.

[For production]

If the upper bus master 30a is outputting a bus request at the time of outputting the bus use request, the cycle control means 19 of the lower bus master 30b extends the output cycle of its own bus use request.

Therefore, in the event of contention, the upper bus master 30a first acquires the bus, and then the lower bus master 30b acquires the bus, but since the next bus request output from the lower bus master 30b is delayed, the upper bus master 30a Buses can be acquired continuously, increasing the DMA transfer speed on the upper side.

〔Example〕

Embodiments of the present invention will be described in detail using FIGS. 1 to 3. FIG. 2 is a time chart of the embodiment, and FIG. 3 is a block diagram of the bus control section of the embodiment.

In this embodiment, as shown in FIG.
An example of changing when there is a conflict with a and extending only the next cycle is shown below.

FIG. 3 shows the bus control section of each lotus mask, and the upper and lower sides have the same configuration, but in the bus master at the highest level, JRQ i is always 11'.

In the figure, 11 is a cycle setting register in which cycle data, here [0110], is stored in advance.

18a and 18b are AND circuits constituting the periodic control means 19, and one input terminal of each is connected to the upper side of the bus request line 20, and *BRQi, which is the bus use request signal on the upper side, is 11". When it is IL+, the value of the period setting register 11 (here, l") is output, and when it is IL+, "O" is output.

Reference numeral 12 denotes a hexadecimal cycle counter, which has load terminals A to B. When the hold terminal is L', that is, when a DMA request and carry RC are on, the data input to terminals A to D is loaded. Ru.

The rest of the configuration is the same as in FIG. 7, and the same operations are performed except that the carry RC cycle is extended by the initial value loaded into the cycle counter 12.

Hereinafter, the periodic control operation and the transfer timing on the upper side resulting from this will be explained with reference to FIG.

Now, the upper bus master 30a and the lower bus master 30
It is assumed that the two terminals and terminals b are performing DMA transfer while mutually acquiring the common bus 32.

In the lower bus master 30b, when this BRQi is '11', that is, when there is no contention, the cycle counter 12 is [011].
01 is loaded and the clock is counted 10 (period TI
), outputs carry RC every time
is held in JKFF 1, dRQO is set to L°, and a bus use request signal is output.

When the upper bus master 30a acquires the right to use the bus,
The main BRQi is set to H' and the main BG is set to L", but when data transfer starts, the main G is set to 11'.

As a result, the bus arbiter 31 (FIG. 4) outputs the bus permission signal again (sets dAcK to "L") when the lower bus master 30b indicates that dRQO is "L", and the lower bus master 30b acquires this signal. , after the bus is released by the upper side (this BBSY is 11'), data is transferred.

In this way, DMA transfer is performed on a time-sharing basis between the upper side and the lower side, but when the output timings of this BR old and this BRQO match, here, the initial value is set to the period counter 12 by the output of the carry RC. When loading *B
If RQi is L, [000 instead of [01101]
01, and after 16 counts of the next cycle (cycle T3
).

As a result, while the next RC output from the lower bus master 30b, and therefore the output of the bus use request, is delayed, the upper nomadic master 30a continuously obtains bus permission.

FIG. 3 shows an example in which the period on the lower side is doubled, and the upper side obtains nos twice in a row until the next period.

Note that if the bus use request signals do not compete in the next cycle, the cycle returns to the same as before, but DMA transfer is usually a continuous transfer of several hundred bytes, and the cycles for the upper and lower sides are different (usually Since T2<TI), contention occurs multiple times during IDMA transfer.

Therefore, the transfer speed on the upper side increases accordingly, and if the cycle T3 on the lower side is further extended significantly, the effect will be greater.

As described above, the transfer speed of the upper bus master when DMA transfers are performed in parallel is improved by the simple periodic control means.

Note that AND circuits 18a and 18b are used as period control means.
However, two sets of cycle setting registers may be provided and switched.

〔Effect of the invention〕

The present invention provides a simple DMA transfer control method for improving the DMA transfer speed of the upper side by extending the output cycle of the bus use request on the lower side when bus use requests conflict in the Imozuru bus arbitration system. The improvements that can be made simply by adding additional circuitry are extremely large.

[Brief Description of the Drawings] Fig. 1 is a principle diagram of the present invention, Fig. 2 is a time chart diagram of the embodiment, Fig. 3 is a block diagram of the bus control section of the embodiment, and Fig. 4 is a diagram of the principle of the present invention.
Figure 5 is an explanatory diagram of the Mozuru type bus arbitration system, Figure 5 is a time chart when there is no contention, Figure 6 is a time chart when there is contention, and Figure 7 is a block diagram of a conventional bus control unit. In the figure, L6, 9.17 is a JK flip-flop, JK
FP, 2.4.5.13.15.18a, 18b are AND circuits, 3.8.16 is an inverter, 7.10 is an open collector type inverter, 11 is a cycle setting register,
12 is a cycle counter, 14 is a flip-flop, 19 is a cycle control means, 20 is a bus request line, 21 is a bus grant line,
30a and 30b are bus masters, 31 is a bus arbiter, 3
2 is a common bus. Fig. Time chart of the embodiment Fig. Bus control unit block diagram of the embodiment Fig. Upper Imozuru 2 bus stop method diagram Fig. Time chart when there is no contention Fig. Time chart when there is contention Fig.

Claims (1)

[Claims] A plurality of bus request signals are outputted at fixed intervals to bus request lines (20) connected in a fixed manner, each acquires the right to use the bus preferentially than the higher connected side, and data is transferred in a DMA manner. In a data processing device equipped with bus masters (30a, 30b), the lower bus master has a cycle control means (19) that extends the output cycle of its own bus use request signal when it competes with the bus use request signal of the upper bus master (30a). (30b), and the lower bus master (30b) is connected to the upper bus master (30b).
A DMA transfer control system characterized by detecting a conflict with a) and extending the output cycle to give priority to the DMA transfer of the higher-order bus master (30a).