JPS63310033A - Multiprocessor diagnostic system - Google Patents

Abstract

PURPOSE:To obtain a multiprocessor system with high reliability by facilitating the check of the performance of connection between each central processing and a main storage device and the check of the connection between each input/ output controller and the main storage device. CONSTITUTION:In receiving a request of a bus acquisition request signal 103-1 by a priority/data transfer control section (PIC) 4, bus use permission signals 105 1 are issued from the PIC 4 to a CPU 2-1. Then the CPU 2-1 starts data transfer with a main storage section 1. When the PIC accepts the request of the bus acquisition request signal 104-1, the bus use permission signal 106-1 is issued from the PIC 4 to the IOC 3-1, which starts the data transfer with the main storage section 1. Each CPU 2-i and each IOC 3-i write data in the main storage section 1 by the data transfer to read the written data. Then the written data is compared with the readout data to conduct the test of the main storage section 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a multiprocessor diagnostic method, and more particularly to initial diagnosis at startup of a multiprocessor system.

BACKGROUND ART Conventionally, in this type of multiprocessor system, only the main central processor section among the central processor sections constituting the multiprocessor system tests the main memory section as an initial diagnosis. In addition, each I/Q (1nput10putput
) The control processor section only diagnoses its own device (for example, diagnoses the flip 70 block, registers, cache, local memory, etc. that are accessed from the processor, and tests the instruction execution of the processor). A connection test was not conducted by data transfer between the main memory and the gate.

In the initial diagnosis at startup of such a conventional multiprocessor system, only the main central processor section tested the main memory section, so other central processor sections other than the main central processor section There is a drawback that the main memory section is not tested and the connectivity between these other central processor sections and the main memory section cannot be checked. Also, each I
Since a connection test using data transfer between the I10 control processor section and the main memory section was not performed, it was not possible to check the connectivity between each I10 control processor section and the main memory section, and the initial diagnosis of the system was not possible. The disadvantage is that it is not possible to detect failures early.

Purpose of the Invention The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional system. It is possible to check gender, expand the scope of diagnosis,
The purpose of this invention is to provide a multiprocessor diagnostic method that can improve the failure detection rate and realize a highly reliable multiprocessor system.

Structure of the Invention A multiprocessor diagnostic method according to the present invention is a multiprocessor diagnostic method for a multiprocessor system configured with a main memory, a plurality of central processing units, and a plurality of input/output control devices, wherein the main memory A data transfer control means is provided for controlling data transfer between the device, the plurality of central processing units, and the plurality of input/output control devices, and when the multiprocessor system is started up, the data transfer control means A feature of the present invention is that a connection test between each device is performed by controlling the transfer.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a multiprocessor system according to an embodiment of the present invention includes a main memory section 1 including a storage control section, and a central processor section (hereinafter referred to as CPtJ) 2-i (i
=1,2. -・-・, n) and l10tiIII
1 processor unit (hereinafter referred to as 10C) 3-B: and a priority/data transfer control unit (hereinafter referred to as PIC) 4. The main storage unit 1 and each CPLJ 2-i are connected by a memory bus 101, and each CPU 2-i and each t
It is connected to oc3-+ by an I10 bus 102. The memory bus 101 and the I10 bus 102 each consist of three types: address lines, data lines, and control l lines.

PtO2 controls the right to use the memory bus 101, the right to use the I10 bus 102, and controls data transfer between the memory bus 101 and the I10 bus 102.

Next, the operation of one embodiment of the present invention will be explained using FIG.

When this multiprocessor system is powered on,
Each CPU 2-i and each 1003-i start self-diagnosis. This self-diagnosis program is normally stored in a ROM (not shown) provided in each device.

10C3-i is equipped with ROM and RO
Some models do not have M, but if ROM is not installed, it is usually CPtJ (master processor).
Under the control of the IOC, a diagnostic program is downloaded from the main memory section 1 into the local memory of the IOC, which is not provided with a ROM.

Each CPU 2-i and each 1003-i outputs a bus acquisition request to the PtO 2 when the self-diagnosis is completed. That is, each CPU2-; outputs a bus acquisition request for the memory bus 101, and each CPU1003-1 outputs a bus acquisition request for the I10 bus 101.
02 and memory bus 101 are output. At this time, the access addresses to the main storage unit 1 from each CPU 2-i and each 1oc3-+ are set so as not to overlap.

In this method, for example, by providing a switch in each device, each CPU2-i and each 10C3-
; The uniqueness of the access address can be easily set.

Bus acquisition request signals 103-i and 104-i are output from each CPU2-; and each 1003-i to PtO2, and PtO2
.

104-i determines the priority order.

If the request of the bus acquisition request signal 103-1 is accepted at PtO2, a bus use permission signal 105-1 is issued from PtO2 to the CPU 2-1, and the CPU 2-1 starts data transfer with the main storage unit 1.

Furthermore, if the request for the bus acquisition request signal 104-1 is passed in PtO2, the bus use permission signal 106-1 is
4 to l0C3-1, and l0C3-1 starts data transfer with main storage unit 1. Similarly, each CPU2-
i and bus acquisition request signal 103 from each toc3-+
-i, 104-i, respectively, bus use permission signals 105-i, 106-i are issued to each CPtJ2-i and each 10C3-i, respectively.

Each CPU 2-i and each 1003-i write data to the main memory section through this data transfer, read the written data, and test the main memory section 1 by comparing the written data and the read data. conduct.

When bus M acquisition request signal 104-i is output from 10C3-i, PIG4 outputs bus use permission signal 1 when both memory bus 101 and I10 bus 102 are permitted to be used.
06-i is returned to l0C3-i. Also, 10C3-
Some i devices have a DMA (direct memory access) function that allows data to be transferred directly to the main storage unit 1 without going through the PIG 4.

Here, the data transfer method is the same as the conventional technology, and will not be particularly explained.

In this way, in the initial diagnosis at startup of a multiprocessor system, data transfer is performed between each CPtJ2-i and the main memory section 1, and each CPU2-i and the main memory section 1 are
By performing a connection test with the main storage unit 1 and each cp
The validity of the connection with u2-1 can be checked. In addition, by performing data transfer between each 1003-1 and the main memory section 1 and performing a connection test between each 10C3-i and the main memory section 1, the main memory section 1 and each Ioc3-t
You can check the validity of the connection between As a result, failures can be detected early in the initial diagnosis of the system, the failure detection rate can be improved, and a highly reliable system can be realized. Furthermore, each CPt
By performing a connection test between J2-i and each 1003-i and the main storage unit 1, the range of diagnosis of the multiprocessor system can be expanded.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, in the initial diagnosis at startup of a multiprocessor system, the main memory, the plurality of central processing units, and the plurality of input/output control units constituting the multiprocessor system are Check the connectivity between each central processing unit and the main storage device and the connection between each input/output control device and the main storage device by transferring data between each device and testing the connection between each device. This has the effect that it is possible to check the performance of the processor, expand the scope of diagnosis, improve the failure detection rate, and realize a highly reliable multiprocessor system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1...Main memory section 2-1 to 2-n...Central processor section (CPU
)3-1 to 3-n...I10υ control processor unit (IOC) 4...Priority/data transfer control unit (PIG) 101...'Memory bus 102. ...I10 bus

Claims (1)

[Claims] A multiprocessor diagnostic method for a multiprocessor system configured by a main storage device, a plurality of central processing units, and a plurality of input/output control devices, the main storage device, the plurality of central processing units, and the plurality of input/output control devices. A data transfer control means for controlling data transfer between the input and output control devices is provided, and when the multiprocessor system is started up, the data transfer control means controls the data transfer to perform a connection test between each device. A multiprocessor diagnostic method characterized by: