JP2767857B2 - Control system having a plurality of processor units - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system having a plurality of processor units, and to an abnormality detection of the processor units.

[Prior Art] In recent years, as engines become more complex and multifunctional, an information processing system is being shared by a plurality of processor units (CPUs). An example of such a system is disclosed in Japanese Patent Publication No. Sho 59-2102. This comprises a plurality of processor units and a shared memory readable and writable in common for each processor unit,
Information is exchanged with each other via the shared memory, and abnormality diagnosis is performed. This abnormality diagnosis is to judge that the processor unit writing to the shared memory is inoperable when the information to be written to the shared memory stops.

[Problems to be Solved by the Invention] However, if the information in the shared memory is not rewritten even if the program operates normally, or if the information writing cycle is slow, it takes time for the abnormality determination to prevent erroneous determination. It takes. That is, it is necessary to monitor for a long time in order to reliably determine whether or not the information to be originally written in the shared memory has stopped. In addition, even when the program runs out of control, the information may be written by accessing the shared memory. Apparently, the writing of the information to the shared memory does not stop, so that the abnormality determination may be delayed or the abnormality determination may not be performed. There is also.

An object of the present invention is to provide a control system having a plurality of processor units that can perform abnormality determination accurately and in a short time.

[Means for Solving the Problems] The present invention provides a plurality of processor units for performing arithmetic processing on data from a sensor, a writable and readable shared memory shared by the processor units, and each of the processor units. A control system comprising a plurality of processor units, each of which is a control target to be connected, wherein each processor unit exchanges each processing information via a shared memory with each other and shares different processing. A storage area dedicated to the check of the processor unit is provided in the shared memory, the processor unit to be checked writes the first data in the storage area dedicated to the check in the shared memory, and the processor unit to be checked is dedicated to the check in the shared memory. The storage area is different from the first data. The processor unit that rewrites the predetermined second data, reads out the data in the check only storage area in the shared memory, and determines that the processor unit to be checked is abnormal when the data is not the second data. Determining, outputting a reset signal from the processor unit to be checked to the processor unit to be checked based on the determination, and detecting an abnormality of the processor unit to be checked based on a signal output from the processor unit to be checked The gist of the present invention is a control system having a plurality of processor units, which is provided with an abnormality detecting unit that performs the abnormality detection.

[Operation] According to the above configuration, the processor unit to be checked writes the first data in the check-only storage area in the shared memory, and the processor unit to be checked stores the first data in the check-only storage area in the shared memory. The predetermined second data different from the above is rewritten.
Further, the processor unit to be checked reads the data in the check only storage area in the shared memory and determines that the checked processor unit is abnormal when the data is not the second data.

Then, based on the determination, a reset signal is output from the processor unit to be checked to the processor unit to be checked.

The abnormality detecting means detects an abnormality of the processor unit to be checked based on a signal output from the processor unit to be checked.

Embodiment An embodiment in which the present invention is embodied in a control device for an automobile engine will be described below with reference to the drawings.

FIG. 1 shows an example of a control device employing a general electronic control method. A sensor group 1 composed of a plurality of sensors is disposed at various parts of the engine and detects an actual operating state of the engine as an electric signal. This sensor group 1 includes a rotation speed sensor 2 that detects the rotation speed of the engine using the rotation of the crankshaft, a rotation angle sensor 3 that detects the rotation angle of the engine by using the rotation of the crankshaft, and a sensor in the intake manifold. An intake pipe negative pressure sensor 4 disposed to detect intake negative pressure, a water temperature sensor 5 to detect engine cooling water temperature
Etc.

The first information processing system 6 includes a first processor unit (hereinafter, referred to as a first CPU) 7, an input interface 8, and an output interface 9. First
The CPU 7 receives signals from the sensors 2 to 4 of the sensor group 1 through an input interface 8 to execute various arithmetic processing, and based on the processing results, outputs an ignition system actuator as a control object via an output interface 9.
Drive control of 10.

The second information processing system 11 includes a second processor unit (hereinafter, referred to as a second CPU) 12, an input interface 13, and an output interface 14. Second
The CPU 12 inputs signals from the sensors 2, 4, and 5 of the sensor group 1 through an input interface 13 to execute various arithmetic processes, and supplies fuel as a control target through an output interface 14 based on the processing results. The drive of the system actuator 15 is controlled.

A shared memory 16 is connected between the first CPU 7 and the second CPU 12, and the shared memory 16 is connected to the first CPU 7 and the second CPU 1.
This is a writable and readable memory shared by the two. For example, an IC memory or the like is used as the shared memory 16, and both CPs are used.
Accessible from U7,12. Then, the CPUs 7 and 12 mutually exchange each processing information via the shared memory 16, and
CPU7 is an ignition system, the second CPU12 is a fuel supply system,
Different arithmetic processing is shared.

Further, a check-only storage area A for detecting an abnormal state of the second CPU 12 is prepared in the shared memory 16 in advance.

The first CPU 7 is connected to a watchdog IC 17 as an abnormality detecting means. The first CPU 7 sends a watchdog signal to the watchdog IC 17, and the watchdog IC 17 monitors the watchdog signal to detect an abnormality of the first CPU 7. To detect. Then, the watchdog IC 17 resets the first CPU 7 when judging that it is abnormal.

The first CPU 7 detects an abnormality of the second CPU 12. Then, the first CPU 7 is reset when the second CPU 12 determines that there is an abnormality.

Next, the operation of the control system thus configured will be described.

FIG. 2 is a flowchart performed by the second CPU 12 at predetermined time intervals. The second CPU 12 calculates the fuel injection time in step 10 and then in step 11 the shared memory
A predetermined value “x” in 16 check-only storage areas A
Write. Therefore, the second CPU 12 writes “x” in the check-only storage area A of the shared memory 16 at predetermined time intervals.

FIG. 3 is a flowchart performed by the first CPU 7 at predetermined time intervals. After executing the arithmetic processing of the ignition timing in step 20, the first CPU 7 reads out the storage contents of the check-only storage area A of the shared memory 16 in step 21 and checks whether the stored data is "x". If it is not "x", "1" is added to the count value N in step 22 (N ← N + 1). Then, the first CPU 7 determines in step 23 whether or not the count value N has reached the predetermined value M. When the count value N reaches the predetermined value M, the first CPU 7 resets the count value N in step 24 (N
= 0) and reset processing of the second CPU 12.

If the data in the check-only storage area A is “x” in step 21, the first CPU 7 proceeds to step 25.
Resets the count value N (N = 0). Then, after processing the steps 23, 24, and 25, the first CPU 7
A value other than “x” is rewritten to the 16 check-only storage areas A.

In this case, in the present embodiment, the data other than “x” is rewritten in the check-only storage area A of the shared memory 16 in step 26, and the data is read out from the check-only storage area A in step 21 at the next processing timing. Between,
Data rewriting of "x" in the storage area A in step 11 in FIG. 2 is performed once.

Therefore, while the second CPU 12 writes “x” in the check-only storage area A of the shared memory 16,
When a value other than "x" is written to the storage area A in the CPU 7, and when the first CPU 7 reads out the stored content, if A @ x continues M times, it is determined that there is an abnormality and the second CPU 12 is reset. Is done.

As described above, according to the present embodiment, the second
The first CPU 7 to be checked writes the first data (a value other than “x”) into the check only storage area A in the shared memory 16 and is checked. The second CPU 12 rewrites predetermined second data (“x”) different from the first data into the check-only storage area A in the shared memory 16 and checks the first CPU 7. The data written by the second CPU 12 in the check only storage area A is read out, and when the data is not the second data (“x”), the second CPU 12 checked is determined to be abnormal. I made it.

Therefore, in the conventional device, if the information in the shared memory is not rewritten even if the program operates normally, or if the writing cycle of the information is slow, it is determined whether the information to be written to the shared memory is stopped. Takes a long time to determine the abnormality in order to make the determination reliably, but in the present embodiment, a check-only storage area A is provided in the shared memory 16 so that the data is not the second data (“x”). Since the second CPU 12 to be checked is determined to be abnormal, the abnormality can be determined in a short time.
Also, in the conventional device, if information is written by accessing the shared memory at the time of program runaway, apparently the information in the shared memory does not stop, and the abnormality determination is delayed,
Although there was a possibility that the abnormality could not be determined, in this embodiment, the second
CPU 12 writes one type of data ("x") into the check only storage area A in the shared memory 16, so that the abnormality determination can be performed accurately.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the shared memory is provided outside the CPU, but may be provided inside the CPU 7 or the CPU 12.
Access to the shared memory may be via a parallel bus or serial communication.

Further, in the above-described embodiment, the process of step 11 (writing of "x" data) is performed once during the process from step 26 (writing of data other than "x") to step 21 (reading of data). However, a timing may be set such that the process of step 11 is performed a plurality of times between steps 26 and 21. The type and quantity of the sensors and actuators to be used are not limited.

Furthermore, in the above embodiment, two information processing systems (two
CPU), but can also be used when using three or more information processing systems (three or more CPUs). An example is shown in FIG. The CPU 7 has n shared memories (18a, 18
.. 18n), information is exchanged with n CPUs (19a, 19b,... 19n). Also, each shared memory 18a, 18b,.
.. 19n have a check only storage area A for detecting an abnormal state of the CPUs 19a, 19b,. The CPU 7 monitors the abnormal state by the watchdog IC 17 and monitors the abnormal state of the CPUs 19a, 19b,... 19n by using the check only storage area A of each of the shared memories 18a, 18b,.

[Effects of the Invention] As described above in detail, according to the present invention, in a control system having a plurality of processor units, abnormality determination can be performed accurately and in a short time. or,
When the processor unit to be checked is in an abnormal state,
The processor unit can be returned to a normal state, and the abnormality of the processor unit to be checked can be reliably detected.

[Brief description of the drawings]

1 is an overall configuration diagram of a control system having a plurality of processor units according to an embodiment, FIG. 2 is a flowchart for explaining an operation, FIG. 3 is a flowchart for explaining an operation, and FIG. 4 is another example. 1 is an overall configuration diagram of a control system having a plurality of processor units. 2 to 5 are sensors, 7 is a first CPU, 10 is an ignition actuator as a control target, 12 is a second CPU, 15 is a fuel supply actuator as a control target, 16 is a shared memory, and A is a check only. Storage area.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G05B 23/02 G06F 11/30 G06F 15/16

Claims (1)

(57) [Claims] 1. A plurality of processor units for arithmetically processing data from a sensor, a writable and readable shared memory shared by each processor unit, and an actuator to be controlled connected to each of the processor units And a processor system in which each processor unit exchanges each processing information with each other via a shared memory and has a plurality of processor units sharing different arithmetic processing. A dedicated storage area is provided, and a processor unit for checking writes the first data to a check dedicated storage area in the shared memory, and the processor unit to be checked stores the first data in the check dedicated storage area in the shared memory. The second predetermined data different from Instead treated, check the data processor unit reads the data of the check-only storage area in the shared memory to the second
The processor unit to be checked is determined to be abnormal when the data is not the data of the above. Based on the determination, a reset signal is output from the processor unit to be checked to the processor unit to be checked, and the output from the processor unit to be checked is output. A control system having a plurality of processor units, comprising: abnormality detection means for detecting an abnormality of the processor unit to be checked based on a signal to be performed.