JPS6330891A - Crt controller - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) The present invention is a CRT controller that holds image data for initialization from a CPU, writes this image data for initialization into memory, and converts it into a video signal. and CRT
This improves the processing efficiency of the CPU.

[Industrial application field]

The present invention relates to a CRT controller, and more particularly, to a CRT controller that sequentially reads image data for one screen from a memory, converts the image data into a video signal, and displays the image data on a CRT.

Generally, in an image display system, one screen worth of image data is stored in a RAM, the image data is sequentially read out from the RAM in accordance with the horizontal and vertical scanning of the CRT, and the read image data is converted into a video signal and then transferred to the CRT. and display.

In such an image display system, a CRT controller is provided to read image data for display from RAM,
The CPU is made to perform RAM replacement and other processing, thereby reducing the speed at which display images can be rewritten in the system.

[Prior Art] FIG. 4 shows a system configuration diagram of an example of a conventional image display system. In the figure, CPU101. Read image data from tRAMll and write image data. Further, image data is read out from the RAM 11 to the CRT controller (hereinafter referred to as rcRTcJ) for display. Each of the above CPU101CRTC12 is a multiplexer 13
Either one accesses RAMII via.

The image data for display read out from the RAM 11 is supplied to the video signal generation circuit 14, where it is converted into primary color signals R, G, and B as video signals. Primary color signals R, G,
B is supplied to the CRT 15 together with a synchronizing signal from the CRTCl 2, and displayed on the CRT 15.

[Problem that the invention seeks to solve]

In the conventional system, CRTCl2 accesses the RAM 11 at a predetermined period during the horizontal scanning period to read image data, and CPtJlo reads R when CRTCl2 is not accessing.
Access AM11.

When clearing the display screen of CRTI 5, such as repainting it to a solid white color, the CPU 10 clears the RAM.
11 and rewrites all image data in RAM II to white image data.

The above-mentioned screen clearing, that is, initialization of the RAM 11, is normally performed within the vertical blanking period, but during this period the CPU 10
Since all the image data in the RAM 11 is rewritten, other processing cannot be performed, and there is a problem in that the processing efficiency of the CPU IO is poor.

The present invention has been made in view of the above points, and
An object of the present invention is to provide a CRT controller that improves processing efficiency.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the CRT controller of the present invention.

In the figure, 1 is an address generating means, which generates at least one address in synchronization with a horizontal synchronization signal and a vertical synchronization signal supplied from a terminal 2.
An address for accessing the memory 3 in which image data for both sides is stored is generated.

The image data read out from the memory 3 is converted into a video signal by the conversion means 4 and supplied to the CRT 5.

The holding means 6 holds initialization image data for erasing the display image supplied by the CPU 7.

When the image data output means 8 is supplied with a signal from the CPU 7 instructing the start of initialization, it takes out the image data for initialization held in the holding means 6 and supplies it to the RAM 3 and the conversion means 4.

The switching means 9 switches access to the memory 3 from reading to writing when a trigger signal is supplied from the CPU 7.

[Effect]

In the present invention, image data for initialization is held in the holding means 6 of the CRT controller, and this initialization data is sequentially written into the memory 3, and is converted into a video signal and supplied to the CRT 5 for display. be done. In other words,
There is no need for the CPU 7 to access each address of the memory 3 and input image data for initialization.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of an image display system to which a CRT controller according to the present invention is applied. In the figure, a CPU 20 corresponding to the CPU 7 shown in the first diagram is CR
The CRTC 21 is connected to a RAM 22 corresponding to the memory 3 and a CRT 23 corresponding to the CRT 5.

For display purposes, the CRTC 21 accesses the RAM 22 at predetermined intervals during the horizontal scanning period, reads out the image data, converts it into primary color signals R, G, and B, which are video signals, and supplies them to the CRT 23 together with the separately generated +111 signal. As a result, the image is displayed on the CR plate 23.

The address and write image data used by the CPtJ20 to access the RAM22 are held in the CRTC21 and
TC21 does not access RAM22 for display
Writing and reading of the RAM 22 is performed during the I period. In addition, the image data for initializing the RAM 22 is a CRTC
21, and CRTC21 stores it in RAM2 for display.
2 is written into the RAM 22, and the image data for initialization is converted into primary color signals R, G, and B and displayed on the CRT 23.

FIG. 3 shows a block system diagram of an embodiment of a CRT controller according to the present invention. In the figure, a clock generation circuit 30
A system clock signal of the image display system is inputted from two terminals of the terminal, and the clock generation circuit 30 generates a dot clock signal corresponding to one dot on the display screen from the system clock signal, and sends this dot clock signal to the horizontal counter 31. It is supplied to each circuit inside the CRTC 21 such as.

The horizontal counter 31 counts the tod clock, and the count value is compared with a predetermined value by the horizontal controller 32.
Here, a pulse is generated every horizontal scanning period. This pulse is counted by a vertical counter 33, and the count value is compared with a predetermined value by a vertical controller 34, where a pulse is generated every vertical scanning period.

The output pulses of the horizontal controller 32 and the vertical controller 34 are supplied to a synchronizing signal generation circuit 35 to generate a horizontal synchronizing signal and a vertical synchronizing signal.

The above-mentioned synchronization signal is supplied to a paralysis and control circuit 36, which will be described later, and the like, and is also supplied to the CRT 23 from terminals 37a and 37b. In addition, when performing superimposed display in which the video generated by this image display system and other video are mixed and displayed, the synchronization signal of the other video is transmitted to the terminal 37.
a, 37b to the synchronization signal generation circuit 35, and C
R-C21 is synchronized.

The interface circuit 40 connects to the CPU 2 via a terminal 41.
0, various control signals are input from the CPU 20, and various control signals output from the CRTC 21 are supplied to the CPU 20. Further, a data bus 42 and an address register 44 are connected to the CPU 20 via terminals 43 and 45, respectively.

The internal register 46, which is the holding means 6, stores the image data for initialization that has entered the data bus 42, the trigger signal, and the CPU 2.
The transfer table 47 stores image data for writing that comes in from the data bus 42, image data that is read from the RAM 22 and is supplied to the CPU 20, and the like. The lookup table (hereinafter abbreviated as rLUTJ) 48 is a fixed table, and the LUTs 49a and 49b are tables that can be rewritten by the CPU 20.

The address supplied from the CPU 20 to the address register 44 specifies which of the internal register 46, transfer table 47, and LUT 49.50 the data, addresses, etc. entering the data bus 42 are supplied to.

Here, the image data consists of pattern data of 8 bits per word in which 1 bit represents 1 dot, and 1 word with 4 bits representing the foreground color and background color.
It is composed of 8-bit color data per word and 8-bit attribute data per word representing characteristics such as underline display, 9 faded display, etc., and includes 12 words of pattern data, 1 word each of color data, and an image of the attribute data. The data represents a display block of 8×12 dots.

The memory access timing controller 50 controls the RAM 22 according to the horizontal synchronization signal, the vertical synchronization signal, and the output pulses of the horizontal controller 32 and the vertical controller 34.
Read/read the control signal that controls writing/reading of wJ.
A control signal is supplied to the write controller 51, a control signal for varying address 1 of the RAM 22 is supplied to the address counter and limiter 52, and a control i1■ signal for transfer control is transferred υ
It is supplied to the control circuit 53.

A read/write controller 51, which is a switching means 9, generates a read enable signal during reading and a write enable signal during writing, and outputs them from a terminal 54 to the RAM 22.
supply to. In addition, an address counter and limiter 52
The address output by the address controller 55 is RA
The terminal 56 is converted into a form for accessing M22.
The data is supplied to the RAM 22 from the RAM 22. This can be done by using dynamic RAM or static RAM as RAM22.
This is because the form of the address depends on whether it is used.

When reading from the RAM 22, the read/write switching circuit 57, which is the image data output means 8, is set to read mode by a control signal from the read/write controller 51, and the image data read from the RAM 22 and input to the terminal 58 is buffered. 59, pattern data,
Color data.

The attribute data are stored in pattern buffers 59a and 59a, respectively.
Color buffer 59b, attribute buffer 59c
are stored separately. The calculation and υ control circuit 36 receives pattern data, color data,
The attribute data is processed to generate color code data in units of dots and supplied to the selector 60.

The selector 60 changes the color code data to red using a table selected from among the LUTs 48, 49a, and 49b according to instructions from the internal register 40.

The data is converted into a total of 12 bits of primary color data, 4 bits each for green and front, and is supplied to the D/Δ conversion circuit 61.

The D/A conversion circuit 61 D/A converts the primary color data into analog primary color signals R, G, and B using the analog power supply supplied from the terminal 62 as a reference, and outputs the CR from the terminal 63.
The image is displayed on the CRT 23. The above LUTs 48 to 49a, buffer 59. Arithmetic and control circuit 36, selector 60. The D/A conversion circuit 61 constitutes the conversion means 4.

The reading of the display image data from the RAM 22 is repeatedly performed by the memory access timing controller 50 at predetermined intervals during the horizontal scanning period. During the period when the display image data is not being read (non-read period), the CPU 20 rewrites the image data in the RAM 22.

In this case, during the non-read period, the memory access timing controller 50 sets the address from the CPU 20 stored in the internal register 46 in the address counter 52, and transfers the image data for wide access stored in the transfer table 47. Set in the control circuit 53. Further, the memory access timing controller 50 switches the read/write controller 51 to output a write enable signal from the terminal 54. At the same time, the address from the address counter and limiter 52 is converted into a form for accessing the RAM 22 by the address controller 55 and is supplied to the RAM 22 via the terminal 56, and the image data for writing in the transfer control circuit 53 is set to read mode. read/write switching circuit 57. It is supplied to the RAM 22 via a terminal 58.

Next, the initialization operation of the RAM 22 will be explained.

Initialization image data output from the CPU 20, ie, pattern data, color data, and trim data, is supplied from a terminal 43 via a data bus 42 to an internal register 46 and stored therein. Furthermore, a trigger signal instructing the start of initialization is supplied from the CPU 20 to the internal register 46 via the data bus and is stored therein.

When the trigger signal output from the internal register 42 is supplied to the memory access timing controller 50, the memory access timing controller 50 sends the control signal to the read/write controllers 1 to 51 and the transfer control circuit 5.
Supply to 3.

Upon receiving the control signal J:, the transfer control circuit 53 takes out the image data for initialization supplied from the internal register 46 and supplies it to the read/write switching circuit 57. At the same time, the read/write controller 51 supplies a write enable signal to the RAM 22 from the terminal 54. Also,
The write mode is set by a control signal from the read/write controller 51, and the image data for initialization selected by the transfer control circuit 53 is supplied from the terminal 58 to the RAM 22 and to five buffers.

Even if the trigger signal is received during the readout period of image data for display from the RAM 22, the address counter and limiter 52 continues to generate addresses. In addition, in the non-reading period, when the horizontal scanning period comes, the address counter and limiter 52 generates an address for accessing the RAM 22 under the control of the memory access timing controller 50 in the same way as when reading image data for display. do. The address generated by the address counter and limiter 52 is sent to the address controller 55 for RA.
It is configured to access M22 and is supplied to RAM 22 via terminal 56.

Therefore, the read/write controller 51 starts outputting the write enable signal due to the input of the signal.
All the image data for one screen in the RAM 22 is rewritten into initialization image data in the vertical scanning period.

At the same time, the pattern data, color data, and attribute data of the initialization image data stored in the buffer 59 are processed by the performance and control circuit 36, and are converted into dot-based color code data. This color code data is converted into 12-bit primary color code data using one of LUTs 48 to 50 in the selector 60, and further converted into primary color signals R, G, and B for initialization in the D/Δ conversion circuit 61. The signal is supplied to the CRT 23. That is, upon receipt of the trigger signal, the CRT 23 performs a display according to the image data for initialization, and the screen is cleared.

In this way, in order to initialize the RAM 22, the CPU 20 transfers the initialization image data and trigger signal to the CRTC2.
1, other processing can be executed during one vertical scanning period when the CRTC 21 initializes the RAM 22, and the processing efficiency of the CPU 20 is improved.

In addition, in the CR-C21, the address counter and limiter 52 performs exactly the same operation at initialization as when reading view angle data for display, and the output of the read/write controller 51 changes from a read enable signal to a write enable signal. Control of the CRTC 21 is simple.

〔Effect of the invention〕

As described above, according to the present invention, the CPU uses 1i for initialization.
By simply outputting jii image data and a trigger signal, one screen worth of image data in the memory can be rewritten into initialization image data, and during this memory initialization period, the CPU
can perform other processing, improving the processing efficiency of the CPU.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the CRT controller of the present invention. FIG. 2 is a block diagram of an embodiment of an image display system to which the CRT controller of the present invention is applied. FIG. 3 is an implementation of the CRT controller of the present invention. Example Block System Diagram FIG. 4 is a block system diagram of an example of a conventional image display system. In the figure, 1 is address generation means, 3 is memory, 4 is conversion means, 5.23 is CRT, 6 is holding means, 7.20 is CPU, 8 is image data output means, 9 is switching means, 46 is 50 is a memory access timing controller, 51 is a read/write controller, 52 is an address counter and limiter, 53 is a transfer control circuit, 55 is an address controller, 57 is a read/write switching circuit, and 61 is a D/A conversion circuit. be. The present invention hFil Riroku72 Figure 1 Figure 2

Claims (1)

[Claims] A memory (where at least one screen worth of image data is stored)
3) is accessed sequentially according to the synchronization signal, and the memory (3) is
) is converted into a video signal and converted to C.
A CRT controller for displaying an image on the RT (5), which is supplied with initialization image data from the CPU (7) for initializing the memory (3) and erasing the displayed image on the CRT (5). A holding means (6) for holding, and a trigger signal instructing to start initialization is supplied from the CPU (7), and the image data for initialization held in the holding means (6) is retrieved and stored in the memory (3). ) and a means (4) for converting image data into a video signal; A CRT controller comprising switching means (9) for sequentially writing initialization image data from data output means (8) into the memory.