JPH0437435B2 - - Google Patents

Description

Detailed Description of the Invention [Summary] The present invention is a CRT controller that reads at least one of color data and attribute data during the horizontal blanking period and uses it for image display, thereby displaying image information during the horizontal display period. It is compatible with systems where data is transmitted and improves CPU processing efficiency.

[Industrial application field]

The present invention relates to a CRT controller, and more particularly, to a CRT controller that sequentially reads one screen worth of image data from a memory, converts the image data into a video signal, and displays the image data on a CRT.

Generally, in an image display system, one screen worth of image data is stored in RAM, the image data is sequentially read out from RAM in accordance with the horizontal and vertical synchronization of the CRT, and the read image data is converted into a video signal and then transferred to the CRT. and display.

In such an image display system, a CRT controller is installed to read image data for display from RAM, and the CPU is used to rewrite RAM and perform other processing, thereby increasing the rewriting speed of display images in the system. etc. are being calculated.

[Conventional technology]

FIG. 5 shows a system configuration diagram of an example of a conventional image display system. In the same figure, CPU10 is RAM1
The image data is read from 1 and the image data is written. Further, image data is read out from the RAM 11 to the CRT controller (hereinafter referred to as "CRTC") for display. The above CPU10,
One of the CRTCs 12 accesses the RAM 11 via the multiplexer 13.

The image data for display read out from the RAM 11 is supplied to the video signal generation circuit 14, where it is converted into primary color signals R, G, and B as video signals. The primary color signals R, G, and B are supplied to the CRT 15 together with a synchronization signal from the CRTC 12, and displayed on the CRT 15.

[Problem that the invention seeks to solve]

In the conventional system, the CRTC 12 accesses the RAM 11 at predetermined intervals during the horizontal display period to read image data for display, and the CPU 10 accesses the RAM 11 during the horizontal blanking period and vertical blanking period.
11 to write image data, etc.

However, for example, in a captain system, there is no distinction between the scanning period and the blanking period.
Image information is transmitted to the CPU 10. Therefore,
CPU10 is RAM11 even during the horizontal display period.
There was a problem in that it was necessary to access the image data to write image data, etc., which the conventional CRTC12 could not handle.

In addition, even if the CPU 10 issues a request to access the RAM 11, the CPU 10 will perform the horizontal blanking period.
There was a problem that access to the RAM 11 was delayed until the vertical blanking period began, resulting in poor processing efficiency of the CPU 10 and slow access to the RAM 11.

The present invention has been made in view of these points, and can be applied to a campus system.
The purpose is to provide a CRT controller that improves CPU processing efficiency.

[Means for solving problems]

FIG. 1 shows a principle block diagram of the CRT controller of the present invention.

In the figure, reference numeral 1 denotes a memory in which at least one screen worth of image data representing one display block is stored, including color data, attribute data, and a plurality of pattern data.

The reading means 2 has one readout per the number of scanning lines of the display block.
During each horizontal blanking period, one or both of the color data and attribute data of all display blocks in one row in the horizontal direction is read, and during each horizontal display period, the remaining one of the color data and attribute data is read out. The pattern data is read out sequentially in a time-sharing manner.

The storage means 3 stores the data read out during the horizontal blanking period for a period of horizontal scanning period corresponding to the scanning line of the display block, stores the data read out during the horizontal display period for a predetermined period, and stores the data read out during the horizontal blanking period for a predetermined period. Output attribute data and pattern data simultaneously.

The converting means 4 converts the image data of the color data, attribute data, and pattern data supplied from the storage means 3 into video signals and causes the CRT 5 to display the video signals.

[Effect]

In the present invention, since at least one of the color data and attribute data is read out during the horizontal blanking period, the time required to access the memory 1 for image display within the horizontal display period is shortened. Furthermore, since at least one of the color data and the attribute data is read out only once per number of scanning lines of the display block, the number of accesses to the memory 1 for displaying one screen image is greatly reduced.

〔Example〕

FIG. 2 shows a block system diagram of an embodiment of the CRT controller according to the present invention. In the figure, the clock signal of the image display system is input to the clock generation circuit 30 from the terminal 29.
0 generates a clock signal corresponding to two dots on the display screen from the system clock signal, and supplies this clock signal to each circuit inside the CRTC, such as the horizontal counter 31.

A horizontal counter 31 counts clock signals, and the count value is compared with a predetermined value in a horizontal controller 32, where a pulse is generated every horizontal scanning period. This pulse is sent to the vertical counter 33
The count value is compared with a predetermined value by the vertical controller 34, and a pulse is generated every vertical scanning period.

Horizontal controller 32, vertical controller 34
Each output pulse is supplied to a synchronization signal generation circuit 35 to generate a horizontal synchronization signal and a vertical synchronization signal. The above synchronization signal is used by the arithmetic and control circuit 3, which will be described later.
6 etc., and is also supplied to the CRT 5 from terminals 37a and 37b. In addition, when performing superimposed display in which the video generated by this image display system and other video are mixed and displayed, the synchronization signal of the other video is sent to the synchronization signal generation circuit 35 from the terminals 37a and 37b. CRTC is synchronized.

The interface circuit 40 is connected via a terminal 41.
It is connected to the CPU, receives various control signals from the CPU, and receives various control signals output from the CRTC. Furthermore, the data bus 42 and address register 44 are connected to the CPU via terminals 43 and 45, respectively.
It is connected to the.

Internal register 46 receives data bus 4 from CPU.
Input image data for initialization, trigger signals, addresses for memory 1 of the CPU, etc. are stored in the transfer table 47, and image data for writing that comes from the CPU from the data bus 42, read from memory 1, Image data etc. that are output and supplied to the CPU are stored. The internal register 46 and the transfer table 47 constitute the holding means 6.
Lookup table (hereinafter abbreviated as “LUT”)
48 is a fixed table and LUT49a, 49b are
This is a table that can be rewritten by the CPU.

The data, addresses, etc. entering the data bus 42 are stored in the internal register 46, transfer table 47, and LUT.
Which of 49 and 50 is supplied depends on the CPU
The address is specified by the address supplied to the address register 44.

Here, image display is performed in units of display blocks. The display block has a first display mode consisting of 4 dots in the horizontal direction x 4 dots in the vertical direction, a second display mode consisting of 8 dots in the horizontal direction x 12 dots in the vertical direction, etc.

Regardless of the first or second display mode, the image data consists of 1 byte 8 bit pattern data where 1 bit represents 1 dot, and 1 byte 8 bits each representing a foreground color and a background color with 4 bits. It consists of bit color data and 1-byte 8-bit attribute data representing attributes such as underline display and blinking display. Note that in the first display mode, 1 byte of pattern data is data for 1 line of 2 display blocks, and in the 1st display mode, 1 display block is represented by 4 bits for each byte of 4 bytes of pattern data. and 12 in the second display mode.
One display block is represented by a byte of pattern data.

Memory access timing controller 50
are a clock signal, horizontal synchronization signal, vertical synchronization signal, horizontal controller 32, vertical controller 34
It is supplied with respective output pulses, and is also supplied with a display mode control signal from an internal register 46.
In response to these signals, a control signal for controlling writing/reading of the memory 1 is supplied to the read/line controller 51, a control signal for varying the address value of the memory 1 is supplied to the address counter and limiter 52, and a control signal for controlling the transfer is supplied to the address counter and limiter 52. A control signal is supplied to the transfer control circuit 53.

The read/line controller 51 generates a read enable signal when reading and a write enable signal when writing, and supplies them to the memory 1 from a terminal 54. Further, the address output from the address counter and limiter 52 is converted by an address controller 55 into a format for accessing the memory 1 and is supplied to the memory 1 from a terminal 56.
This is because the format of the address differs depending on whether dynamic RAM or static RAM is used as the memory 1.

The above horizontal controller 32, vertical controller 34, internal register 45, memory access timing controller 50, read/line controller 51, address counter and limiter 52,
The address controller 55 constitutes the reading means 2.

Further, the image data read out from the memory 1 for display is supplied from the terminal 58 to the buffer 59 which is the storage means 3, and the pattern data, color data, and attribute data are sent to the pattern buffer 59a, color buffer 59b, and attribute data, respectively. They are stored separately in the view buffer 59c. The arithmetic and control circuit 36 performs arithmetic processing on the pattern data, color data, and attribute data supplied from the buffer 59, generates color code data in units of dots, and supplies the data to the selector 60.

The selector 60 uses the table selected from the LUTs 48, 49a, and 49b by the display from the internal register 40 to change the color code data to red, red,
It is converted into a total of 12 bits of primary color data, 4 bits each for edge and blue, and supplied to the D/A conversion circuit 61.
The D/A conversion circuit 61 D/A converts the primary color data into analog primary color signals R, G, and B based on the analog power supply supplied from the terminal 62, and supplies them to the CRT 5 from the terminal 63. The image is displayed. LUT48-49 above
b, a buffer 59, an arithmetic and control circuit 36, a selector 60, and a D/A conversion circuit 61 constitute the conversion means 4.

FIG. 3 shows a detailed block system diagram of an embodiment of the essential parts of the CRT controller. In this figure, the same parts as in FIG. 2 are designated by the same reference numerals.

In FIG. 3, the horizontal counter 31 has terminal 7.
0, the clock signal a shown in FIG. 4A comes in,
The horizontal counter 31 counts this clock signal a and sends the count value to the horizontal controller 32.
supply to. Note that two dots are displayed on the display screen in one period of the clock signal a.

The horizontal controller 32 generates a horizontal clear signal whose count value corresponds to one horizontal scanning period, clears the horizontal counter 31, and also clears the horizontal counter 31.
In the display mode shown in FIG. 4, timing signals b, c, d and timing signal e shown in FIG. 4B, C, D, and E, respectively, are generated. Timing signal b is a signal for instructing the output of a pattern address, and is generated every eight clock cycles during the horizontal display period, and its pulse width is one clock cycle. The timing signal c is a signal for instructing the output of a color address, and rises one clock period after the falling edge of the timing signal b, and has a pulse width of two clock periods. Timing signal d is a signal that displays the output of the attribute address, and rises to L level during the horizontal display period and to H level during the horizontal blanking period, and has a pulse width of 34 clock cycles. The timing signal e is the same signal as the timing signal a and instructs the output of pattern, color, and attribute data.

Furthermore, the horizontal controller 32 generates pulses with a horizontal scanning period and outputs them from the terminal 71 to the synchronizing signal generating circuit 3.
Supply to 5. Note that during the period from the fall of the timing signal b to the rise of the timing signal c, a timing signal similar to the timing signal b for reading out the pattern data of the next raster when performing smoothing is output.

The horizontal clear signal output from the horizontal controller 32 is supplied to the vertical counter 33, which counts the horizontal clear signal and supplies the count value to the vertical controller 34.
When the count value reaches a value corresponding to one vertical scanning period, the vertical controller 34 generates a vertical clear signal to clear the vertical counter 33, and also generates a pulse corresponding to the vertical scanning period and sends it from the terminal 72 to the synchronizing signal generation circuit 35. supply

Further, the horizontal clear signal is supplied to a raster counter 73 that constitutes the memory access timing controller 50, and the raster counter 73 counts the horizontal clear signal and supplies the count value to the raster decoder 74. In the first display mode, the raster decoder 74 generates a gate signal at H level during the period when the count value is "3" and supplies it to the AND circuit 75, and also when the count value is "4".
When this occurs, a raster clear signal is generated and supplied to the clear terminal CLR1 of the raster counter 73.
In addition, the clear terminal CLR2 of the raster counter 73
is supplied with a vertical clear signal. As a result, the rath counter 73 is cleared to "0" immediately before the start of vertical scanning, and thereafter cleared to "0" every four horizontal scanning periods.

The AND circuit 75 is supplied with the timing signal d output from the horizontal controller 32, and the gate circuit 75 outputs the last fourth raster of the display block when the count value of the raster counter 73 is "3" in the first display mode. Take out the timing signal d during the horizontal blanking period immediately after is displayed,
It is output as a timing signal f.

The timing signal b output from the horizontal controller 32 is transmitted to the memory access timing controller 50.
The pattern start address register 76 in the internal register 46 and the pattern buffer 59
The timing signal c is supplied to the color start address register 77 and the color buffer 59b via the memory access timing controller 50. The timing signal e is passed through the memory access timing controller 50 to a pattern buffer 59a, a color buffer 59b,
It is supplied to each attribute buffer 59c. Furthermore, the timing signal f output from the AND circuit 75 of the memory access timing controller 50 is supplied to the attribute start address register 78 and the attribute buffer 59c. pattern start address register 76,
Each of the color start address register 77 and the attribute start address register 78 inputs the start address stored therein to the address counter 80 in the address counter and limiter 52 at the rising edge of each of the supplied timing signals b, c, and f. and save the address values of the address counter 80 at the falling edge of each of the timing signals b, c, and f. The address counter 80 increments the address value by a clock signal a supplied from a terminal 81, and outputs the address value from a terminal 82 to the address controller 55 shown in the second figure.
Here, the data is supplied to the memory 1 in a form in which the memory 1 is accessed.

Memory 1 is a pattern data area of approximately 7k bytes,
A color data area of about 0.35k bytes and an attribute area of about 0.35k bytes are each set according to the address, and one address writes/reads 2 bytes of 16 bits of data.

The pattern data, color data, and attribute data read out from the memory 1 according to the output address value of the address counter 80 are transferred from the terminal 58 shown in FIG. 3 to the pattern buffer 59a and the color buffer 59b via the data bus 83. , and are supplied to each of the attribute buffers 59c.

The pattern buffer 59a latches pattern data for 2 bytes and 4 display blocks that arrive during the H level period of the timing signal b, and transfers the pattern data from the terminal 84a to the arithmetic and control circuit 36 shown in the second figure during the H level period of the timing signal e. supply to. The color buffer 59b latches 2 bytes of color data for 4 display blocks of 4 bytes that arrive during the H level period of the timing signal c every 1 clock cycle.
One byte at a time is supplied from the terminal 84b to the calculation and control circuit 36 during the H level period of the timing signal e. The attribute buffer 59c latches the attribute data for 68 bytes and 68 display blocks that arrive during the H level period of the timing signal f, and performs calculation and processing one byte at a time from the terminal 84c during the H level period of the timing signal e. It is supplied to the control circuit 36.

By the way, one period of clock signal a is approximately
At 350nsec, the memory cycle of memory 1 is approximately
It is 350nsec. Furthermore, 1 on the CRT display screen
The horizontal display period is 136 clock periods, the horizontal blanking period is 46 clock periods, and the vertical display period is 204 horizontal scan periods, and the vertical blanking period is 204 horizontal scan periods.
58 horizontal scanning periods.

In the first display mode, 34 bytes of pattern data and 34 bytes of color data are used in one horizontal display period.
68 bytes, attribute data 68 bytes total
170 bytes need to be read from memory 1,
Further smoothing would require a total of 204 bytes. Therefore, if memory 1 reads/writes 1 byte 8 bits at 1 address, smoothing cannot be performed in 1 horizontal scanning period of 182 clock cycles, so memory 1 reads/writes 2 bytes 16 bits at 1 address. It is configured to do so.

Also, out of the horizontal display period of 136 clock cycles,
34 bytes of pattern data are read out in 17 clock cycles, 68 bytes of color data are read out in 34 clock cycles, and attribute data is read out during the horizontal blanking period. Therefore, the remaining 85 clock periods of the horizontal display period are available for use by the CPU.

Note that another image data is read out from the memory 1 in four clock cycles from the fall of the timing signal c to the rise of the timing b in FIG. 4C to generate a video signal different from the video signal described above. It is also possible to switch between two types of video signals and display two types of images.

Also, if you read out the attribute data for each line, it is necessary to read out the attribute data for each line in the first display mode.
13872 (=68×204) bytes of attribute data must be read. However, in the above embodiment, since the attribute data is read during the horizontal blanking period for every 4 lines, 1
It is only necessary to read 3468 bytes of attribute data per screen, and the number of accesses to memory 1 is 25% of the above, or 1734 times.

Note that when the CPU writes image data to the memory 1, information such as the write address output by the CPU and the number of transferred words is supplied from the data bus 42 to the read address register in the internal register 46 and stored. The image data is supplied from the data bus 42 to the transfer table 47 and stored therein, and furthermore, a trigger signal instructing the start of access from the CPU is supplied to the internal register 46 through the data bus 42 and stored therein.

In response to the input of the trigger signal, the memory access timing controller 50 generates a write timing signal that becomes H level when all of the timing signals b, c, and f are at L level, and when the write timing signal is at H level, the memory access timing controller 50 addresses the read address register. is loaded into the address counter 80 and incremented at the clock cycle, and the obtained write address is supplied to the memory 1.

At the same time, the read/line controller 5
4 is a memory access timing controller 50
memory 1 from terminal 54 in response to a control signal from
Supplies a write enable signal to Also, when the write timing signal is at H level, the image data in the transfer table 47 is sequentially supplied to the transfer control circuit 53 every clock cycle, and is selected here for read/write.
The signal is supplied to the light switching circuit 61. The read/write switching circuit 61 is the read/write controller 5
The image data is supplied to the memory 1 from the terminal 58.

As a result, image data from the CPU is sequentially written into the memory even during the horizontal display period.

Note that when image data of the same number of words as the number of transferred words is written to or read from the memory 1, the memory access timing controller 5
0 forces the read/write timing signal to the L level, thereby stopping writing and reading from the memory 1 by the CPU.

In this manner, the CPU can supply the write address and write data of the memory 1 to the CRTC when an access request for the memory 1 is generated, and then perform other processing, improving the processing efficiency of the CPU. Further, since writing or reading from the memory 1 by the CPU is performed during the horizontal display period, writing or reading is performed at high speed, and the efficiency of use of the data bus and address bus between the CRTC and the memory 1 is improved. Furthermore, the structure of the image display system can be simplified without requiring a circuit such as a multiplexer.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to write image data to the memory by the CPU within the horizontal display period, it is possible to support a captain system, and it is possible to improve the processing efficiency of the CPU.
Memory can be accessed at high speed.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the CRT controller of the present invention, FIG. 2 is a block diagram of an embodiment of the CRT controller of the present invention, and FIG. 3 is a partial block diagram of the CRT controller shown in Figure 1.
FIG. 4 is a time chart of signals of various parts of the circuit shown in FIG. 3, and FIG. 5 is a block system diagram of an example of a conventional image display system. In the figure, 1 is a memory, 2 is a reading means, and 3 is a memory.
4 is a storage means, 4 is a conversion means, 5 is a CRT, 46 is an internal register, 47 is a transfer table, 50 is a memory access timing controller, 51 is a read/write controller, 52 is an address counter and limiter, 53 is a transfer control circuit, 55 is an address controller, 57 is a read/write conversion circuit, 61 is a D/A conversion circuit, 73 is a raster counter, 74 is a raster decoder, 76 is a pattern start address register, 77 is a color start address register, and 78 is an attribute. It is an address register.

Claims (1)

[Scope of Claims] 1. Sequentially accessing a memory in which at least one screen worth of image data representing one display block including color data, attribute data, and a plurality of pattern data is stored according to horizontal synchronization and vertical synchronization, In a CRT controller that converts image data read from the memory into a video signal and displays it on a CRT, the color of all display blocks in one horizontal row is changed during one horizontal blanking period for each scanning line number of the display block. reading means for reading either or both of data and attribute data, and sequentially reading out the remaining one of the color data and attribute data and pattern data in each horizontal display period in a time-sharing manner; and the horizontal blanking. The data read out during the period is stored for a period of a horizontal scanning cycle equal to the number of scanning lines of the display block, the data read out during the horizontal display period is stored for a predetermined period, and the color data and attribute data are stored. and storage means for simultaneously outputting pattern data.
controller.