JPS63308423A - Multiprocessing type synchronizing circuit - Google Patents

Abstract

PURPOSE:To increase a processing speed by calculating a real frame phase from the stored value of a storage means and the counted value of a common counter and outputting it. CONSTITUTION:The common counter 3 is in a free-rum state and the storage means 1 is stored with a common counter value when a frame synchronizing pattern conforms. The stored value of this stored means 1 is held until a step- out state is entered. An arithmetic circuit 5 calculates the real frame phase from the stored value and common counter value and outputs it. Said operation is carried out by multiplex lines. Thus, count-up operation is not performed by using a RAM, so reading and writing need not be performed in one time slow by time-division processing and the processing speed is increased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a synchronization circuit for multiplexed lines in digital communication, and in particular, to a multiplexing circuit suitable for increasing processing speed and increasing the number of lines to be processed in a multiplexed line. Regarding synchronous circuits.

[Conventional technology]

The conventional multiprocessing type synchronous circuit is 5 Japanese Patent Application Laid-Open No. 56-11955.
As described in Publication No. 5, the frame phase of each line is stored in RAM.
and sequentially store R for each time slot of the multiplexed line.
A series of operations such as reading AM data, incrementing the value, writing the data to RAM, and changing the frame phase are performed for each line to perform one-hour side load processing.

[Problem that the invention seeks to solve]

The above conventional technology performs RA within one time slot for each line.
Since it is necessary to read and write M
The operating speed of the RAM is limited, and synchronization processing cannot be performed at a faster speed than the operating speed of the RAM. Therefore, there is a problem in that the number of processing lines of multiplexed lines cannot be increased.

An object of the present invention is to provide a multiprocessing type synchronous circuit that can increase the multiprocessing capability of the synchronous circuit.

[Means for solving problems]

The above purpose is to use a counter common to each multiplexed line and frame synchronization pattern detection for each line in a multiprocessing type synchronization circuit that synchronizes multiplexed line digital signals into which frame synchronization codes are independently inserted. This is achieved by providing a storage means for storing a value indicating the phase, and an arithmetic circuit that calculates and outputs the actual frame phase using the stored value of the storage means and the count value of the common counter.

[Effect]

The common counter is in a free running state.

The storage means stores a common counter value when the frame synchronization patterns match. The value stored in this storage means is saved until synchronization is lost. The arithmetic circuit calculates the actual frame phase from this stored value and the common counter value and outputs it. The above operation is performed for each multiplexed line.

In this way, in the present invention, since the count-up operation is not performed using the RAM, there is no need to perform reading and writing in one time slot by time-sharing processing, and the processing speed can be increased. Also, there is no possibility of loss of synchronization due to a RAM shift error.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a multi-processing type synchronous circuit according to an embodiment of the present invention. In FIG. 1, 1 is a storage element, 2 is a multiple counter, 3 is a common counter, 4 is a comparator, 5 is a real frame phase calculation circuit, 7 is a synchronization protection circuit, 9 is an OR gate, 10.11 is an AND gate It is.

The multiplexed input data to be subjected to frame synchronization processing is input to the pattern detection circuit 8. Pattern detection circuit 8
outputs a signal to that effect when detecting a frame synchronization pattern. Further, a clock synchronized with the input data is input to the common counter 3 and the multiplex counter 2. The common counter 3 is in a free-running state and sends the operating phase value of the counter (common counter value) to the comparator 4, the actual frame phase calculation circuit 5, and the storage element 1. Moreover, the multiplex counter 2.

The signal that specifies the multiplexing phase for frame synchronization processing is
output to the storage element 1, and the storage element 1 reads out the previously stored operating phase value of the common counter according to the specified signal,
It is output to the real frame phase calculation circuit 5 and comparator 4. The comparator 4 compares the two operating phase values received from the common counter 3 and the storage element 1, and if they match, passes the frame identification phase signal through the OR gate 9 (AND) 1
Output to 0.11. 10.11 respectively performs the logical product of the output of this OR gate 9, the detection signal from the pattern detection circuit 8, and the inverted signal of the detection signal.

Output to the synchronization protection circuit 7. The AND gate 10 outputs a pattern match signal, and the AND gate 11 outputs a pattern mismatch signal. Synchronous protection circuit 7
performs a frame protection operation at the multiplex level and transmits a hunting designation signal to the common counter 3 and OR gate 9.

Next, the operation of the multiprocessing type synchronous circuit configured as described above will be explained with reference to FIGS. 2 and 3.

FIG. 2 is an explanatory diagram of the operation during the hunting operation. Figure 2 shows a case in which frame synchronization is performed for each frame at the multiplex level for input data in which n (an integer of n > 2) frames each consisting of m (an integer of m ≥ 1) blocks are multiplexed. FIG. The multiplex counter value is a signal output from the multiplex counter 2 to the storage element 1, and specifies which frame data is currently being input in the frame-multiplexed input data series. . The common counter value advances by one step relative to the increment of the multiplex counter 2, and has the function of separating blocks of multiplexed input data. It is sent to the real frame phase calculation circuit 5 and the storage element 1. The common counter value does not match the actual phase in the outer frame included in the multiplexed input data.

In Figure 2, the n-th frame in the multiplexed input data (the multiplex counter value in the figure is expressed as 3-1 since the starting point is 0) falls out of synchronization, and the multiplexed The frame synchronization pattern in the converted input data is detected, and the value of the common counter 3 at that time is stored in the storage element 1. First, the n-th frame of the multiplexed signal is initially out of synchronization, and at this time, the multiplex counter value is n -1, but in the reception phase of the data of the A write operation state is entered, and the value "m-1" of the common counter 6 is written into the storage area of the th frame in the memory element 1. At this time, the frame synchronization pattern is detected in the pattern detection circuit 8 for the input data D, and the output is sent to the synchronization protection circuit 7 through the AND circuits 10 and 11.
receives the frame, and determines whether to end the hunting operation for the frame numbered. If the input data v does not have a frame synchronization pattern as shown in FIG. The value "0" of counter 3 is written.

Here, if the input data F is a frame synchronization pattern, the pattern detection circuit 8 converts the pattern detection output signal A
Sends to ND circuits 10 and 11, protection circuit 7 AND
A match signal is received from the circuit 10, a flag is set to end the hunting operation in the first frame, and the hunting operation is ended. In the block next to the block in which the noching operation has been completed, as shown in FIG. 10'', which is the value of the common counter 3 at the time of frame synchronization pattern detection, is read from the storage area.

FIG. 3 is an explanatory diagram of the operation in the synchronous operation state. In Figure 3, the first frame (multiple counter value is n-1
) is in a synchronous operation state, and at this time, the storage element 1 is in a read state and outputs the value "0" of the common frame counter 3 stored during the hunting operation, and this signal is sent to the comparator 4.
is input to the actual frame phase calculation circuit 5. When the common frame counter 3 increments and the common counter value becomes "0".

The comparator 4 emits a frame identification phase signal, and the AND circuits 10 and 11 detect whether the pattern detection output signal of the pattern detection circuit 8 matches or does not match.
The synchronization protection circuit 7 transmits the match signal/mismatch signal indicating the result.
receives the signal and determines whether to proceed to hunting operation. The synchronization protection circuit 7 performs a synchronization protection operation at multiple levels, controls the transition between the hunting operation state and the synchronous operation state, and has the function of issuing an out-of-synchronization alarm to the outside of one circuit. . The actual phase in each multiplexed frame is determined by reading out the phase at which the frame synchronization pattern was detected during the hunting operation from the storage element 1, and converting the read data from the common counter value from the incrementing common counter 3. It is found by subtracting.

As described above, in this embodiment, the storage element 1 performs only one of reading and writing operations during one time slot of the multiplexed signal, and in the synchronous operation state, the storage element 1 always performs reading and writing operations. is performing an action.

〔Effect of the invention〕

According to the present invention, since no RAM is used, the processing speed is not limited by the operating speed of the RAM.

Therefore, the processing speed can be increased, and the processing ability of the synchronous circuit is improved.

[Brief explanation of drawings]

, 8. Fig. 1 is a block diagram of a multiprocessing type synchronous circuit according to an embodiment of the present invention, Fig. 2 is a diagram illustrating transition from a hunting operation state to a synchronous state, and Fig. 3 is an explanation of synchronous operation. This is a diagram showing the 1......Memory element 3...Common counter 5...
・・・・・・Real frame phase calculation circuit, -//

Claims (1)

[Claims] 1. In a multiprocessing synchronization circuit that synchronizes multiplexed line digital signals into which frame synchronization codes are independently inserted, a counter common to each multiplexed line and a frame synchronization pattern detection phase for each line are used. 1. A multiprocessing type synchronous circuit comprising: a storage means for storing a value indicated by the common counter; and an arithmetic circuit for calculating and outputting an actual frame phase based on the stored value of the storage means and the count value of the common counter.