JPS63305437A - System state tracer - Google Patents

Abstract

PURPOSE:To make the handling of a system state tracer easy by providing the tracer with a memory circuit previously connected to a common system bus and its control circuit. CONSTITUTION:Necessary information is applied from a system bus to the memory circuit 1 as data and the system bus information is successively stored in the memory circuit 1 in each state cycle. When an event signal is applied to an operation control circuit 3, and circuit 3 switches writing operation to reading operation by regarding the state as the final storage information and also switches address information applied from a counter circuit 2 to that applied from a system bus 20. A read control circuit 4 is driven by a request from a CPU module 21 and the state information stored in the memory circuit 1 is outputted to the system bus 20. Consequently, the information excellent in the reproducibility of an event and extremely significant to event analysis can be obtained and its handing can be made easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system state tracer, and particularly to a system state tracer for operating analysis in a component-based computer system constituted by various boards organized by buses.

[Conventional technology]

Conventionally, this type of system state tracer is performed by adding equipment such as an emulator device that simulates a central processing function or a logic state analyzer to a common system bus in a computer system.

[Problem that the invention seeks to solve]

In the conventional system state tracer mentioned above,
Since the system is configured to connect separate devices, it requires complicated connection work and skill and specialized knowledge.

Additionally, changes in operating speed and device-specific limitations may confuse analysis results. Additionally, if a fault occurs in a remote location that requires system behavior analysis,
This method has disadvantages in that it requires the dispatch of specialized personnel and the preparation of expensive equipment.

An object of the present invention is to provide a system state tracer that is easy to install by providing a memory circuit and its control circuit that are connected in advance to a common system bus.

[Means for solving problems]

The system state tracer of the present invention includes a memory circuit that stores all state information on the system bus according to state cycles, an operation control circuit that controls the start and stop of storage, and a system bus that is controlled by the operation control circuit. The controller is configured to include a control circuit and a control circuit that receives address information from the controller.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a microcomputer system in which the system state tracer of FIG. 1 is implemented. Figure 1 shows a memory circuit 1, an address counter circuit 2, and an operation control port! ! !
3, a read control circuit 4 and a system bus interface 5. In the microcomputer system shown in FIG. 2, a CPU module 21, a memory module 22, an interface module 23, and a system state tracer 24 are connected to a system bus 20.

The operation of this system state tracer is roughly divided into two modes: one is a mode that stores system state information on the system bus in real time (state trace mode), and the other is a mode that stores the stored state information in real time. This is a mode (read mode) for reading information. The system operation in FIG. 2 is performed between the CPU module 21 and the memory module 22, and between the CPU module 21
This consists of the exchange of information between the system bus 20 and the interface module 23, and all of that information is transmitted via the system bus 20. System state tracer 2 operating in state trace mode
4 transfers the information appearing on the system bus to the internal memory circuit 1 without affecting the operation of the system.
Store it in. Then, by giving the event to be analyzed to the system state tracer as an event signal, the state trace mode is automatically stopped and the read mode is entered. The system state tracer 24 in the read mode operates as if it were one memory module when viewed from the CPU module 21, and when the information is read, it is possible to obtain system state information up to the event to be analyzed.

Next, proceeding with the explanation of the two modes of operation in FIG. A read switching operation is performed. In the state trace mode, address information given to the memory circuit 1 is given from the counter circuit 2, and the memory circuit 1 performs a write operation. Counter circuit 2 detects state cycles from system bus 20 and counts them to provide address information to memory circuit 1 that is updated for each state. The memory circuit 1 is given necessary information as data from the system bus, and the memory circuit 1 is sequentially given each state cycle.
System bus information is stored in .

Next, when an event signal is given to the operation control circuit 3, the operation control circuit switches the memory circuit 1 from the write operation to the read operation, using the state at that time as the last stored information, and also transfers the address information from the counter circuit 2 to the system system. Switch to address information given from bus 20. C.P.
In response to a request from the U module 21, the read control circuit 4
operates, and the state information stored in the memory circuit 1 is output to the system bus 20. The above is the operation in the output mode.

〔Effect of the invention〕

As explained above, the present invention stores the state information of a system without affecting the operation of the system, and can arbitrarily read out the state information up to the event to be analyzed. It has excellent reproducibility and can provide extremely significant information for event analysis. In realizing the system state tracer of the present invention,
Because it has a simple configuration, it can be produced at a lower cost than analysis equipment, and it can be built into the system in advance, or even if it is added as an option after operation, it is easy to handle and is necessary even for non-experts. This has the effect of allowing you to extract relevant information.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
1 is a block diagram of an example of a microcomputer system implementing the system state tracer shown in FIG. 1...Memory circuit, 2...Address counter circuit,
3... Operation control circuit, 4... Readout control circuit, 5.
...System bus interface, 20...System bus, 21...CPU module, 22...Memory module, 23...Interface module, 2
4...System state tracer. 1st figure 2I! r

Claims (1)

[Claims] A memory circuit that records all state information on the system bus according to the state cycle, an operation control circuit that controls the start and stop of recording, and an operation control circuit that records address information given from the system bus under the control of this operation control circuit. 1. A system state tracer comprising: a read control circuit for reading out stored contents by applying signals to a circuit.