JPS63304658A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPS63304658A
JPS63304658A JP62140854A JP14085487A JPS63304658A JP S63304658 A JPS63304658 A JP S63304658A JP 62140854 A JP62140854 A JP 62140854A JP 14085487 A JP14085487 A JP 14085487A JP S63304658 A JPS63304658 A JP S63304658A
Authority
JP
Japan
Prior art keywords
substrate bias
output
substrate
circuit
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62140854A
Other languages
Japanese (ja)
Inventor
Shuichi Imazeki
今関 秀一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62140854A priority Critical patent/JPS63304658A/en
Publication of JPS63304658A publication Critical patent/JPS63304658A/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the rise of a substrate potential caused by ionized current, by providing a substrate bias generating circuit which operates only when it is necessary to increase the capability of the substrate bias. CONSTITUTION:Between voltages VDD, VSS, two MOS transistors Q1, Q2 are connected in series, and a terminal 3 is formed, which is connected to a substrate bias generating circuit 4. To gate electrodes 1, 2 of the MOS transistors Q1, Q2, driving signals are input with a differential system, and an output signal is output to an output terminal 3. By driving the subsrtate bias generating circuit 4 with this output signal, the substrate bias generating circuit 4 operates to increase the capability of the substrate bias, only when the output signal is output to the output terminal 3. The rise of the substrate bias is restrained, thereby.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子によって構成される回路に関する。[Detailed description of the invention] [Industrial application field] TECHNICAL FIELD The present invention relates to a circuit constituted by semiconductor elements.

〔従来の技術〕[Conventional technology]

通常の半導体装置の出力回路は第2図に示した様にVD
DとVssO間に2つのMOSトランジスタQ、、Q、
を直列接続したもので、MOSトラ一28フ ンジスタQ1.Q2の夫々のゲート電極1.2には駆動
信号が夫々差動力式で入力され、出力端子3に出力信号
が出力される。
The output circuit of a normal semiconductor device is VD as shown in Figure 2.
Two MOS transistors Q, ,Q, between D and VssO
are connected in series, with 28 MOS transistors Q1. A drive signal is inputted to each gate electrode 1.2 of Q2 in a differential force type, and an output signal is outputted to an output terminal 3.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

また、基板バイアス発生回路の技術は広く知られ℃おり
、通常の半導体回路の基板は通常−2〜−4Vに逆バイ
アスされているが、出力回路によシ出力信号が出力され
た時、すなわち、トランジスタQ、もしくはQ2のどち
らかがオンした時、オンしたトランジスタにより、基板
にホールの注入が行なわれ、基板電位の上昇ひいては内
部回路の娯動作をひきおこす原因となる。この現象は、
イオン化電流による不良として知られているが、このイ
オン化電流の大きさはトランジスタの電流能力に比例す
る。従って電流能力を請求される為に必然的にトランジ
スタのサイズが大きくなる出力回路においてはその影響
は顕著となる。
In addition, the technology of substrate bias generation circuits is widely known, and the substrate of an ordinary semiconductor circuit is normally reverse biased to -2 to -4V, but when an output signal is output to the output circuit, i.e. , transistor Q, or Q2 is turned on, holes are injected into the substrate by the turned-on transistor, causing an increase in the substrate potential and, in turn, causing an idle operation of the internal circuit. This phenomenon is
This is known as a defect caused by ionization current, and the magnitude of this ionization current is proportional to the current capability of the transistor. Therefore, this effect becomes significant in output circuits where the size of transistors is inevitably large due to the current capability required.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の目的は出力端子に出力信号が出力された場合に
生ずるイオン化電流による基板電位の上昇を防ぐ効果的
な手段を提供することにある。
An object of the present invention is to provide an effective means for preventing an increase in substrate potential due to an ionization current generated when an output signal is output to an output terminal.

本発明は、基板バイアス回路を内蔵する半導体装置にお
いて、2つのMOSトランジスタの直列接続を主たる構
成要素とする出力回路であって、その出力端子の出力信
号を使って駆動される基板バイアス回路を有し、出力端
子に出力された時に発生する、イオン化電流によシ基板
電位が上昇した時、同時にその出力信号によシ基板バイ
アス回路を駆動することにより、基板バイアス回路の能
力を増して基板電位の上昇を押えることを特徴とする半
導体回路である。
The present invention relates to a semiconductor device incorporating a substrate bias circuit, which includes an output circuit whose main component is two MOS transistors connected in series, and which is driven using an output signal from an output terminal of the output circuit. When the substrate potential rises due to the ionization current generated when it is output to the output terminal, the output signal drives the substrate bias circuit at the same time, increasing the capability of the substrate bias circuit and increasing the substrate potential. This is a semiconductor circuit characterized by suppressing the rise in .

−〔実施例〕 本発明の一実施例を第1図に基づき説明する。- [Example] An embodiment of the present invention will be described based on FIG.

VDDとVssの間に2つのMOS)ランジスタQ、、
Q、を直列接続し、出力端子3を形成する。
Two MOS) transistors Q between VDD and Vss.
Q, are connected in series to form an output terminal 3.

更に出力端子3を基板バイアス発生回路4に接続する。Further, the output terminal 3 is connected to a substrate bias generation circuit 4.

この時MOSトランジスタQl 、Qzの夫々のゲート
電極1.2に駆動信号が夫々差動力式で入力され、出力
端子3に出力信号が出力されるが、この出力信号により
基板バイアス発生回路4を駆動する仁とによシ、出力端
子3に出力信号が出力した時のみ基板バイアス発生回路
4が動作して基板バイアスの能力を増すことによシ、基
板バイアスの上昇を押えるようにしである。
At this time, drive signals are input to the gate electrodes 1.2 of each of the MOS transistors Ql and Qz in a differential force type, and an output signal is output to the output terminal 3. This output signal drives the substrate bias generation circuit 4. In addition, the substrate bias generating circuit 4 operates only when an output signal is output to the output terminal 3 to increase the substrate bias capability, thereby suppressing an increase in the substrate bias.

本発明の他の実施例を第3図に示す。第1図に示した基
板バイアス発生回路4として、基板とVss間に直列に
接続した2つのMOSトランジスタQ3 、 Q4とコ
ンデンサCを用いた実施例である。
Another embodiment of the invention is shown in FIG. This is an embodiment in which two MOS transistors Q3 and Q4 and a capacitor C are connected in series between the substrate and Vss as the substrate bias generating circuit 4 shown in FIG.

〔発明の効果〕〔Effect of the invention〕

既に示した様に、半導体装置の動作に有害な、イオン化
電流の発生は出力端子に出力信号が出力された時に起き
やすく、基板バイアスの上昇を招くが、本発明によシ基
板バイアスの能力を増す必要な時のみ働く基板バイアス
発生回路を設けることにより、基板バイアスの上昇を効
果的に押えることができる。
As already shown, the generation of ionization current, which is harmful to the operation of semiconductor devices, tends to occur when an output signal is output to the output terminal, leading to an increase in substrate bias.However, the present invention improves the ability of substrate bias. By providing a substrate bias generation circuit that operates only when an increase in substrate bias is necessary, an increase in substrate bias can be effectively suppressed.

これまで、NチャンネルMO8)ランジスタについて説
明したがPチャンネルMOSトランジスタの場合にも、
同様に適用できるのは明らかである。
So far, we have explained N-channel MO8) transistors, but also in the case of P-channel MOS transistors.
It is clear that the same applies.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一拠施例を示す回路図、第2図は従来
の出力回路を示す回路図、第3図は本発明の応用例を示
す回路図である。 Q1〜Q4・・・・−・MOSトランジスタ、1〜3・
・・・・・節点、4・・・・・・基板バイアス発生回路
、5・−・・・・基板、C・−・・・・コンデンサを示
す。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional output circuit, and FIG. 3 is a circuit diagram showing an application example of the present invention. Q1-Q4...-MOS transistor, 1-3.
. . . Node, 4 . . . Substrate bias generation circuit, 5 . . . Substrate, C .

Claims (1)

【特許請求の範囲】[Claims] 基板バイアス回路を内蔵する半導体装置において、2つ
のMOSトランジスタの直列接続を主たる構成要素とす
る出力回路であって、その出力信号を使って基板バイア
ス回路を駆動することを特徴とする半導体回路。
A semiconductor device incorporating a substrate bias circuit, which is an output circuit whose main component is two MOS transistors connected in series, and whose output signal is used to drive the substrate bias circuit.
JP62140854A 1987-06-04 1987-06-04 Semiconductor circuit Pending JPS63304658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62140854A JPS63304658A (en) 1987-06-04 1987-06-04 Semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62140854A JPS63304658A (en) 1987-06-04 1987-06-04 Semiconductor circuit

Publications (1)

Publication Number Publication Date
JPS63304658A true JPS63304658A (en) 1988-12-12

Family

ID=15278284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62140854A Pending JPS63304658A (en) 1987-06-04 1987-06-04 Semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS63304658A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812748B2 (en) 2002-07-09 2004-11-02 Renesas Technology Corp. Semiconductor device having substrate potential detection circuit less influenced by change in manufacturing conditions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812748B2 (en) 2002-07-09 2004-11-02 Renesas Technology Corp. Semiconductor device having substrate potential detection circuit less influenced by change in manufacturing conditions

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