JPS63302530A - Circuit board for large current and hybrid integrated circuit thereof - Google Patents

Circuit board for large current and hybrid integrated circuit thereof

Info

Publication number
JPS63302530A
JPS63302530A JP62137746A JP13774687A JPS63302530A JP S63302530 A JPS63302530 A JP S63302530A JP 62137746 A JP62137746 A JP 62137746A JP 13774687 A JP13774687 A JP 13774687A JP S63302530 A JPS63302530 A JP S63302530A
Authority
JP
Japan
Prior art keywords
circuit
aluminum
solder
copper
foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62137746A
Other languages
Japanese (ja)
Other versions
JP2564487B2 (en
Inventor
Kazuo Kato
和男 加藤
Tatsuo Nakano
辰夫 中野
Shinichiro Asai
新一郎 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP62137746A priority Critical patent/JP2564487B2/en
Publication of JPS63302530A publication Critical patent/JPS63302530A/en
Application granted granted Critical
Publication of JP2564487B2 publication Critical patent/JP2564487B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0263High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3473Plating of solder

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the concentration of currents according to the little dispersion of partial wall thickness, to stabilize quality as a hybrid integrated circuit for high power, to simplify the manufacturing process of the circuit and to reduce manufacturing cost by mounting solder to a copper circuit pattern section through which large currents flow. CONSTITUTION:Layers consisting of at least aluminum foil and copper foil are laminated onto a good thermal conductive insulating layer 5 on metallic substrates 1 to respectively form circuits, and solder 10 is set up to sections as the large current circuits of the copper circuits 1. The copper foil sections 1 as lower layers consisting of dissimilar metallic composite foil and aluminum foil sections functioning as aluminum bonding posts 3 as upper layers are laminated onto a base metal 6. Circuits composed of eutectic solder 10 are shaped to the sections, through which large currents flow, in the copper foil sections 1. Heat spreaders 2, etc., on which power transistors 7 are placed are loaded with the eutectic solder 10. These power transistors 7, etc., are connected to the aluminum bonding posts 3 by aluminum wires 9, thus forming the circuits.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は銅回路パターンの局所に半田?形成した回路を
設けて、大電流の必要な回路部分となすインバーターで
代表されるパワーモジュールのワイヤーポンディング可
能な大電流用回路基板及びその混成集積回路に関するも
のである。
[Detailed Description of the Invention] (Field of Industrial Application) Does the present invention apply solder locally to copper circuit patterns? The present invention relates to a wire bondable large current circuit board of a power module, typified by an inverter, which is provided with a formed circuit to form a circuit portion that requires large current, and a hybrid integrated circuit thereof.

(従来の技術) パワーモジュール用の混成集積回路基板としてはセラミ
ックス基板が従来から多く使用されて来たが、その回路
形成が貴金属ペーストによるため、シート抵抗が大キく
、近年のパワーモジュールの大電流化には不向きになっ
て来ている。従って従来は鋼等の金属薄板を回路に半田
付し、この大電流化に対応し℃いた。またこれに代る基
板としてアルミニウムと鋼の両方の金属が露出した回路
を有し、絶縁層に高熱伝導性の樹脂を用b)た金属ぺ−
ス基板が開発された(特開昭58−48432号公報)
(Prior technology) Ceramic substrates have traditionally been widely used as hybrid integrated circuit boards for power modules, but since the circuits are formed using precious metal paste, the sheet resistance is large, and the large size of power modules in recent years has It has become unsuitable for electric current. Therefore, in the past, a thin metal plate such as steel was soldered to the circuit to cope with this increase in current. Alternatively, a metal plate with a circuit in which both aluminum and steel metals are exposed and a highly thermally conductive resin is used as an insulating layer can be used as an alternative substrate.
A new board was developed (Japanese Unexamined Patent Publication No. 58-48432).
.

この基板は銅の露出した回路の一部で半田付による回路
形成例えばヒートスグレツダーや外部リ−yの接続を行
ない、アルミニウムの露出した回路の一部で半導体ベア
ーチツゾとの超仔波振動アルミニウムワイヤーボン2イ
ングな行なう様に設計されている。
This board uses a part of the circuit with exposed copper to form a circuit by soldering, such as connecting a heat sink or an external relay, and a part of the circuit with exposed aluminum to connect a semiconductor bare chisel to ultrasonographic vibration aluminum. It is designed to perform wire bong 2-ing.

またアルミニウムおよび銅回路パターンの露出部の銅回
路の局所に厚付きメッキを施すことにより、大成流通・
成用回路や半導体、発熱素子を設けたハイパワー用混成
集積回路がある(特開昭62−2587号公報)。
In addition, by applying thick plating to the exposed parts of the aluminum and copper circuit patterns, Taisei Ryutsu Co., Ltd.
There is a high-power hybrid integrated circuit provided with a component circuit, a semiconductor, and a heating element (Japanese Patent Laid-Open No. 62-2587).

しかしながら、この方法ではメッキ時間が長い7tめメ
ッキの肉厚Vこバラツキが生じ易く、大成流を必要とす
る回路部分の認銅消厚みの一定のものができず、従って
・・イパワー用混成集積回路としての品質の安定性に欠
ける欠点があった。
However, this method tends to cause variations in the wall thickness of the 7t plating, which takes a long plating time, and it is not possible to achieve a uniform thickness of copper plated in circuit parts that require large currents. The drawback was that the quality of the circuit lacked stability.

(発明が解決しようとする問題点) 本発明は、かかる欠点を解決するものであり、大成流の
流れる銅回路パターン部位に半田を設けて大電流回路と
することにエリ、部分的な肉厚のバラツキが少ない回路
となっているため電流集中がなく、ハイパワー用混成集
積回路としての品質が安定し、さらに回路の製造工程の
闇路化、製造コストの低減につながるワイヤーfンデイ
ング可能な大成流用回路基板及びその混成集積回路を提
供するものである。
(Problems to be Solved by the Invention) The present invention solves these drawbacks, and has the advantage of providing a large current circuit by providing solder on the copper circuit pattern portion where large currents flow. Because the circuit has little variation in current, there is no current concentration, and the quality as a high-power hybrid integrated circuit is stable.Furthermore, the circuit is wire-wrappable, which reduces the circuit manufacturing process and reduces manufacturing costs. The present invention provides a reused circuit board and its hybrid integrated circuit.

(問題点を解決するための手段) すなわち本発明は、 1、金属基板上の良熱伝導性絶縁層を介して少なくとも
アルミニウム箔と銅箔とからなる層を積層して夫々回路
を形成し、前記銅回路の大電流回路となる部位に半田を
設けたことを特徴とする大電流用回路基板 2、金属基板上の良熱伝導性絶縁層に少なくともアルミ
ニウム回路と大成流用回路となる部位に半田を設けた銅
回路を形成してなる回路基板に半導体を配置し、該半導
体とアルミニウム回路とをアルミニウム線で接続したこ
とを特徴とする大電流用混成集積回路及び 6、 金属基板上の良熱伝導性絶縁層に少なくともアル
ミニウム回路と大成流用回路となる部位に半田を設けた
銅回路な形成してなる回路基板に半導体を配置し、該半
導体とアルミニウム回路とをアルミニウム線で接続した
回路基板に外部リード端子を接続し、前と回路基板をデ
ル状シリコン系樹脂およびエポキシ系樹脂組成物にて封
止したことを特徴とする大電流用混成集積回路、で、ち
る。
(Means for Solving the Problems) That is, the present invention has the following features: 1. A circuit is formed by laminating layers each consisting of at least aluminum foil and copper foil via an insulating layer with good thermal conductivity on a metal substrate; A large current circuit board 2 characterized in that solder is provided at a portion of the copper circuit that will become a large current circuit, and a high thermally conductive insulating layer on a metal substrate is provided with solder at least at an aluminum circuit and a portion that will become a Taisei diversion circuit. A hybrid integrated circuit for large current, characterized in that a semiconductor is arranged on a circuit board formed with a copper circuit provided with a copper circuit, and the semiconductor and an aluminum circuit are connected with an aluminum wire, and 6. Good heat resistance on a metal substrate. A circuit board in which a semiconductor is arranged on a circuit board formed of a conductive insulating layer formed with a copper circuit with solder provided at least in the aluminum circuit and the portion that will become the Taisei diversion circuit, and the semiconductor and the aluminum circuit are connected with an aluminum wire. A hybrid integrated circuit for large current, characterized in that an external lead terminal is connected and the front and circuit board are sealed with a delta-shaped silicone resin and an epoxy resin composition.

以下本発明の詳細な説明する。The present invention will be explained in detail below.

、g1図(a+ 、(t))及び(C)は、本発明の混
成集積回路を表わす実施例の平面図と1iffJ図であ
る。第1図(+))はベース金属6上には絶縁層5を介
して異種金属複合箔からなる丁暑が銅消部1、上層がア
ルミニウム・トンrイングポスト3となるアルミニウム
、6都が積層されている。また肩箔部10大電流が流れ
る部位には共晶半田10からなる回路が形成されている
。またこの共晶半田10にエリパワートランジスター1
が載置されたヒートスゾレツダ。
, g1 (a+, (t)) and (C) are a plan view and an 1iffJ diagram of an embodiment representing a hybrid integrated circuit of the present invention. Fig. 1 (+) shows that on the base metal 6, through the insulating layer 5, there is a copper conductor part 1 made of composite foil of different metals, the upper layer is aluminum, and the aluminum tunneling post 3 is made of aluminum. Laminated. Further, a circuit made of eutectic solder 10 is formed in a portion of the shoulder foil portion 10 through which a large current flows. Also, this eutectic solder 10 has an elipower transistor 1
Heat Szoretsuda on which was placed.

2やその他発熱素子例えばトランジスター、FKT。2 and other heating elements such as transistors and FKTs.

IC等、具体的にはダイオード8が塔載されている。さ
らにこれ等のパワートランジスター7とダイオード8は
、アルミニウムワイヤー9によりアルミニウムポンディ
ングボスト3に接続されて回るアルミニウムボンディン
グボスト3、その上層に銅消部1が形成されており、そ
の他は、第1図(kl)と同様である。
An IC or the like, specifically a diode 8, is mounted thereon. Further, these power transistors 7 and diodes 8 are connected to an aluminum bonding post 3 by an aluminum wire 9 and rotated, and a copper dissipating part 1 is formed on the upper layer thereof, and the other parts are as shown in FIG. (kl).

次に第2図は第119(b)回路の外部リード端子半田
付部4で外部リード端子11を接続した後、回路の周囲
をパッケージ12で覆い、絶縁層5より上層部をパッケ
ージ12の上端までデル状シリコン系樹脂13とエポキ
7樹脂組成物14で封止した回路の断面図である。なお
第2図は、第1図(C)回路も同様な操作を行つもので
ある。
Next, in FIG. 2, after connecting the external lead terminal 11 at the external lead terminal soldering part 4 of the circuit 119(b), the circuit is covered with a package 12, and the layer above the insulating layer 5 is connected to the upper end of the package 12. 3 is a cross-sectional view of a circuit sealed with a delta-shaped silicone resin 13 and an epoxy 7 resin composition 14. FIG. Note that the circuit shown in FIG. 2 performs the same operation as the circuit shown in FIG. 1 (C).

本発明に用いるベース金属板として(ハ、良熱伝導性を
有する、アルミニウム、銅、鉄やそれらの合金が用いら
れる。また熱伝導・曲の良い7絶縁層はアルミナ、ベリ
リア、″トロンナイトライド、マグネシア、シリカおよ
び窒化アルミニウム等の良熱伝導性無機フィラーを例え
ば60重161以上含んだ熱硬化性樹脂等があり、その
厚みも耐電圧が許される限り薄いものが良く、通常は2
0 pm以上は必要である。
The base metal plate used in the present invention (c) is made of aluminum, copper, iron, or an alloy thereof, which has good thermal conductivity.The insulating layer 7, which has good thermal conductivity and flexibility, is made of alumina, beryllia, tron nitride, etc. , thermosetting resins containing good thermal conductivity inorganic fillers such as magnesia, silica, and aluminum nitride, for example, 60wt.
0 pm or more is necessary.

次に絶縁層を介してアルミニウム箔と鋼箔の両方の金属
が露出した回路を形成する方式には2つあり、その1つ
はアルミニウム銅りラッP滴又はアルミニウム箔上に鋼
メッキして形成した箔、あるいはアルミニウム箔に亜鉛
もしくはニッケルを介して銅を順次メッキした箔を絶縁
物上に張り合せた基板をエツチングにより回路形成した
ものである。
Next, there are two ways to form a circuit in which the metals of both aluminum foil and steel foil are exposed through an insulating layer. A circuit is formed by etching a substrate on which a foil made of aluminum or aluminum foil plated with copper via zinc or nickel is laminated onto an insulator.

さらに本発明の混成集積回路の大電流回路となる部位は
、銅箔に半田を形成することにより目的を達することが
でき、半田の肉厚は、大電流通電容量に合わせて自由に
変化させることができる。
Furthermore, the purpose of the part of the hybrid integrated circuit of the present invention that becomes a large current circuit can be achieved by forming solder on copper foil, and the thickness of the solder can be freely changed according to the large current carrying capacity. Can be done.

AMへの半田形成方法は、回路基板を半田バスへ浸漬す
る方法及びクリーム状半田をfl眉の必要個所に印判し
、加熱・リフローする方法のいづれであってもよい。半
田の肉厚は、特に制限するものではないが、65μm超
、好ましくは45μm〜1500μm1さらに好ましく
は50μm〜600μmである。肉厚が65μm以下で
は大電流通電容量が得られず、また上限は別に制限はな
いが、通常の混成集積回路としては、1500μm程度
が限度である。
The method for forming solder on the AM may be either a method of dipping the circuit board in a solder bath or a method of stamping creamy solder on the required portions of the fl eyebrows and heating and reflowing the solder. The thickness of the solder is not particularly limited, but is more than 65 μm, preferably 45 μm to 1500 μm, and more preferably 50 μm to 600 μm. If the wall thickness is less than 65 μm, a large current carrying capacity cannot be obtained, and although there is no particular upper limit, the upper limit for a normal hybrid integrated circuit is about 1500 μm.

次に回路を封止するゲル状シリコン系樹脂は例えばシリ
コン對脂単独または、良熱伝導性を有する充填剤含有シ
リコン粛脂のいずれでもよい。さらにエポキシ樹脂、組
成物は耐湿性、低応力を持つ組成物であれば何んら限定
するものでない。
Next, the gel-like silicone resin for sealing the circuit may be, for example, either a silicone resin alone or a filler-containing silicone resin having good thermal conductivity. Furthermore, the epoxy resin and composition are not limited in any way as long as they are moisture resistant and have low stress.

すなわち本発明の混成集積回路に用いる基板はアルミニ
ウムと肉厚鋼箔の両方の金属が露出した回路基板であり
、露出した銅箔の大電流が流れる部位に半田を形成させ
た回路が存在するため、電流容量的に充分で、うり、大
成流が流せられる。また、発熱素子を固着する部分も肉
厚半田となっているため、発熱素子を半田付すればヒー
トスゾレツダーにもなる。
In other words, the substrate used in the hybrid integrated circuit of the present invention is a circuit board in which both aluminum and thick steel foil metals are exposed, and there is a circuit with solder formed on the exposed copper foil where a large current flows. It has sufficient current capacity and can flow large currents. Furthermore, since the part that fixes the heating element is also made of thick solder, it can also be used as a heat solder by soldering the heating element.

その他では、発熱素子(パワー素子)の発熱看、サイズ
、基板の熱伝導率が問題となり、従って熱伝導匪の良い
絶縁層を有する金属基板が本発明てLるハイパワー用混
成集積回路として必要となる。
In other cases, the heat generation of the heating element (power element), the size, and the thermal conductivity of the substrate are issues, and therefore a metal substrate having an insulating layer with good thermal conductivity is necessary for the high power hybrid integrated circuit according to the present invention. becomes.

(実施例) 以下実施例により詳細に説明する。(Example) This will be explained in detail below using examples.

実施例1 第4図(a)、(b)に示すごとく、基板は、ベース金
属板6に絶縁層5を介して10μmの鋼箔と10μmの
アルミニウム箔からなる異種金属複合箔により構成され
、さらに大電流回路部分には肉厚120μmの共晶半田
10が形成されている。次にこの基板を用いて半田付き
の必要な部分(端子取付部、パワートランジスターやダ
イオードの取付部)にスクリーン印刷(ICより半田ペ
ーストを印刷した。次に8 X 8 X 002ttr
xのパワートランジスター6ケと1.5 X L5 X
 O,2電のダイオード6ケを第1図に示す個所に置き
、半田リフロー炉を通して半田付けした。
Example 1 As shown in FIGS. 4(a) and 4(b), the substrate was composed of a dissimilar metal composite foil consisting of a 10 μm steel foil and a 10 μm aluminum foil on a base metal plate 6 with an insulating layer 5 interposed therebetween. Furthermore, eutectic solder 10 with a thickness of 120 μm is formed in the large current circuit portion. Next, using this board, screen printing (solder paste was printed from the IC) on the parts that required soldering (terminal attachment areas, power transistor and diode attachment areas).Next, 8 x 8 x 002ttr
6 x power transistors and 1.5 x L5 x
Six O.2 current diodes were placed at the locations shown in Figure 1 and soldered through a solder reflow oven.

次に400μmの直径を有するアルミニウム太線を用い
、このパワートランジスターからアルミニウムゼンrイ
ンデボストに超音1&憑動法でワイヤーポンディングし
て配線した。同様にパワートランジスターからダイオー
ド・\もワイヤーボンディングした。
Next, using a thick aluminum wire having a diameter of 400 .mu.m, wire bonding was performed from this power transistor to the aluminum Zenr indebost using the ultrasonic method. Similarly, I wire-bonded the diode from the power transistor.

次に14本の外部リード端子を半田付した後パッケージ
を回路にかぶせシリコン樹脂を第2図の様にアルミニウ
ムワイヤーやパワートランジスターがかくれるまで注入
し、硬化させデル状にした。
Next, after soldering the 14 external lead terminals, the package was placed over the circuit, and silicone resin was injected until it covered the aluminum wires and power transistors as shown in Figure 2, and was cured to form a del-shape.

その後エポキシ樹脂2組酸物をその上から注入し、硬化
させた。
Thereafter, two sets of epoxy resins were injected with an acid compound from above and cured.

以上の工程を経ることにより第6図に示す電気回路を有
する、モーター制御用大電力パワーモジュール(インバ
−ター)を完成させた。このインバーターはコレクタ絶
縁型のため取付けが簡単で許容電流を3OAにすること
が出来た。
By going through the above steps, a high-power power module (inverter) for controlling a motor was completed, having the electric circuit shown in FIG. This inverter is collector insulated, so installation is easy and the allowable current can be 3OA.

実施例2 第4図(C)に示すごとく、アルミニウム箔を絶縁層5
側に形成し、しかも共晶半田の肉厚を150μmとした
以外は、実施例1と同様の操作を行いモーター制御用大
゛1カパワーモジュール(インバーター)を得た。この
インバーターは、許容電流を4OAとすることができた
Example 2 As shown in FIG. 4(C), aluminum foil was used as an insulation layer 5.
A large one-power module (inverter) for motor control was obtained by carrying out the same operation as in Example 1, except that the thickness of the eutectic solder was 150 μm. This inverter was able to provide an allowable current of 4OA.

実施例6 j44図(a) 、 (kl)に示す回路基板において
、大電流回路部に肉厚共晶半田10が形成されていない
10μmの鋼箔と40μmのアルミニウム箔から構成さ
れた絶縁金属基板を用いた。
Example 6 In the circuit board shown in j44 (a) and (kl), the insulated metal board was composed of a 10 μm steel foil and a 40 μm aluminum foil, in which the thick eutectic solder 10 was not formed in the large current circuit part. was used.

まずこの基板の大′に/1rf、回路部分及び半田付の
必要な部分(端子末付部パワートランジスターやダイオ
ード取付部)にスクリーン印刷により半田ペーストを印
刷した。次に8 X 8 X 0−2gmのパワートラ
ンジスター6ケと1.5 X 1.5 X O,2肩冨
のダイオード6ケを第1図に示す個所に置き、半田リフ
ロー炉を通して半田付けした。半田ペーストの大電流回
路部分の厚みは半田リフロー後150μmであった。
First, solder paste was printed on the large part of this board by screen printing on the circuit part and the parts where soldering was required (power transistor and diode mounting part) on the large part of this board. Next, six power transistors of 8 x 8 x 0-2 gm and six diodes of 1.5 x 1.5 x O, 2 shoulder thickness were placed at the locations shown in Figure 1 and soldered through a solder reflow oven. The thickness of the large current circuit portion of the solder paste was 150 μm after solder reflow.

この半導体を塔載した基板を用いた以外は実施例1と同
様にアルミニウム太線によるワイヤーボンディング及び
外部リード端子の半田付及びパッケージングを行って、
第6図に示す電気回路を有する、インバーターを得た。
Wire bonding with thick aluminum wires, soldering of external lead terminals, and packaging were performed in the same manner as in Example 1, except that the substrate on which this semiconductor was mounted was used.
An inverter having the electric circuit shown in FIG. 6 was obtained.

このインバーターは許容電流を4OAとすることが出来
た。
This inverter was able to provide an allowable current of 4OA.

(比較例) 第4図の′A箔が10μmで半田による大電流回路を形
成させなかった他は実施例と同様の基板を用いて、第3
図に示すインバ−ターを製造した。
(Comparative example) Using the same board as in the example except that the 'A foil in Fig. 4 was 10 μm and no large current circuit was formed by soldering, a third
The inverter shown in the figure was manufactured.

まず実施例と同じパワートランジスターを16X 16
 X 0−8mの銅製ヒートスゾレツダーに高温半田で
半田付した。このもの?実施例と同様に半田ペーストを
スクリーン印刷した基板上に置き、ダイオードと共に半
田をリフローし半田付した。
First, use the same power transistor as in the example, 16×16
It was soldered to a 0-8m copper heat solder using high-temperature solder. This thing? As in the example, a solder paste was placed on a screen-printed board, and the solder was reflowed and soldered together with the diode.

以後の工程は実施例と同様にしてパッケージした完成品
を得た。このインバーターは鋼箔厚みが10μのと薄い
ため、許容電流は10A以下であった。
The subsequent steps were carried out in the same manner as in the examples to obtain a packaged finished product. Since this inverter had a thin steel foil thickness of 10 μm, the allowable current was 10 A or less.

(発明の効果) 以上のとおり本発明はアルミニウムと銅回路パターン上
の、1liily’ffi部の大電流が流れる部位に半
田を形成した回路パターンを有する絶縁金属基板におい
て半導体等とアルミニウム回路とをアルミニウム線で接
続した回路であり、tlJ大電流を流せる様にセラミッ
ク基板における金属薄板による回路の補強の必要がない
(2)ヒートスプレッダ−として半田を用いると基板の
半田回路との密着が有利である、(3)アルミニウムの
ワイヤー、tFンrイングポストがあるため、アルミニ
ウム線による半導体のワイヤーがンデイン〆が信頑性良
く出来る。特に数百μmの直径を有する太線のアルミワ
イヤーは、パワートランジスター等の大電流を流す半導
体素子の結線には欠かせないものであり、この太線のア
ルミワイヤーがワイヤーボンディング出来る利点がある
(Effects of the Invention) As described above, the present invention has an insulated metal substrate having a circuit pattern in which solder is formed in the 1liily'ffi portion where a large current flows on the aluminum and copper circuit pattern. It is a circuit connected with a wire, so there is no need to reinforce the circuit with a thin metal plate on the ceramic board so that a large tlJ current can flow. (2) When solder is used as a heat spreader, it is advantageous to have close contact with the solder circuit on the board. (3) Since there is an aluminum wire and a tF ring post, it is possible to connect the semiconductor wire with the aluminum wire with good reliability. In particular, thick aluminum wire with a diameter of several hundred μm is indispensable for connecting semiconductor devices such as power transistors that flow large currents, and this thick aluminum wire has the advantage of being able to be wire bonded.

更に熱伝導性の良い絶縁層を有する金属基板を用いるこ
とに=9(4)従来のセラミック基板を用いた場合より
も熱伝導性が良くなり、パワーモジュールQ大゛戒力化
に有利で、ちる。しかも(5)セラミック基板を用いた
パワーモジュールではセラミックが割れ易いため鋼のニ
ッケルメッキ板等のベース金属をセラミック基板に半田
付は等で接着せねばならないが、金属基板ではベース金
属が第2図に示す様にパッケージの下部に配置されるた
め、新しくベース金属を置く必要がない等の利点がある
Furthermore, using a metal substrate having an insulating layer with good thermal conductivity = 9 (4) The thermal conductivity is better than when using a conventional ceramic substrate, which is advantageous for increasing the power module Q, Chiru. Moreover, (5) in a power module using a ceramic substrate, the base metal, such as a nickel-plated steel plate, must be bonded to the ceramic substrate by soldering or the like because the ceramic is easily broken; however, in the case of a metal substrate, the base metal is As shown in the figure, since it is placed at the bottom of the package, it has the advantage that there is no need to place a new base metal.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)及び(C)は本発明のハイパワー
用混成集積回路の平面図および断面図であり、第2図は
第1図の集積回路を樹脂封止した集積回路の断面図を表
わす。また第5 t’iUは電気回路図である。 次に第4図(a)、(b)及び(C)は実装前の基板を
表わす平面図と断面図である。 符号1・・・鋼箔部、2・・・ヒートスゾレッダー、3
・・・アルミニウムがンデイングポスト、4・・・外部
リーy端子半田付部、5・・・絶縁層、6・・・ベース
金属板、7・・・パワートランジスター、8・・・ダイ
オード、9・・・アルミニウム線・fヤー、10・・・
共感半田、11・・・外部IJ −y端子、12・・・
パッケージ、13・・・ビル状シリコン系樹、脂、14
・・・エポキシ甜脂組成物 特許出願人 電気化学工業株式会社 喜3A 箋4鴛(a)
FIGS. 1(a), (b), and (C) are a plan view and a sectional view of a high-power hybrid integrated circuit of the present invention, and FIG. 2 is an integrated circuit in which the integrated circuit of FIG. 1 is sealed with resin. represents a cross-sectional view of Further, the fifth t'iU is an electric circuit diagram. Next, FIGS. 4(a), (b), and (C) are a plan view and a sectional view showing the board before mounting. Code 1... Steel foil part, 2... Heatsolder, 3
... Aluminum mounting post, 4... External lead Y terminal soldering part, 5... Insulating layer, 6... Base metal plate, 7... Power transistor, 8... Diode, 9 ...Aluminum wire, f-ya, 10...
Sympathetic solder, 11... External IJ -y terminal, 12...
Package, 13... Building-shaped silicone resin, resin, 14
... Epoxy sugar beet composition patent applicant: Denki Kagaku Kogyo Co., Ltd. Ki3A Paper 4 Raku (a)

Claims (3)

【特許請求の範囲】[Claims] (1)金属基板上の良熱伝導性絶縁層を介して少なくと
もアルミニウム箔と銅箔とからなる層を積層して夫々回
路を形成し、前記銅回路の大電流回路となる部位に半田
を設けたことを特徴とする大電流用回路基板。
(1) Layers consisting of at least aluminum foil and copper foil are laminated via a good thermally conductive insulating layer on a metal substrate to form a circuit, respectively, and solder is provided at a portion of the copper circuit that will become a high current circuit. A circuit board for large currents that is characterized by:
(2)金属基板上の良熱伝導性絶縁層に少なくともアル
ミニウム回路と大電流用回路となる部位に半田を設けた
銅回路を形成してなる回路基板に半導体を配置し、該半
導体とアルミニウム回路とをアルミニウム線で接続した
ことを特徴とする大電流用混成集積回路。
(2) A semiconductor is placed on a circuit board formed by forming at least an aluminum circuit and a copper circuit with solder in a portion that will become a large current circuit on a good thermally conductive insulating layer on a metal substrate, and the semiconductor and the aluminum circuit are arranged on a circuit board. A high current hybrid integrated circuit characterized by connecting the two with an aluminum wire.
(3)金属基板上の良熱伝導性絶縁層に少なくともアル
ミニウム回路と大電流用回路となる部位に半田を設けた
銅回路を形成してなる回路基板に半導体を配置し、該半
導体とアルミニウム回路とをアルミニウム線で接続した
回路基板に外部リード端子を接続し、前記回路基板をゲ
ル状シリコン系樹脂およびエポキシ系樹脂組成物にて封
止したことを特徴とする大電流用混成集積回路。
(3) A semiconductor is placed on a circuit board formed by forming at least an aluminum circuit and a copper circuit with solder in a portion that will become a large current circuit on a good thermally conductive insulating layer on a metal substrate, and the semiconductor and the aluminum circuit are arranged on a circuit board. 1. A hybrid integrated circuit for large current, characterized in that an external lead terminal is connected to a circuit board which is connected with an aluminum wire, and the circuit board is sealed with a gel-like silicone resin and an epoxy resin composition.
JP62137746A 1987-06-02 1987-06-02 Circuit board and hybrid integrated circuit thereof Expired - Lifetime JP2564487B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62137746A JP2564487B2 (en) 1987-06-02 1987-06-02 Circuit board and hybrid integrated circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62137746A JP2564487B2 (en) 1987-06-02 1987-06-02 Circuit board and hybrid integrated circuit thereof

Publications (2)

Publication Number Publication Date
JPS63302530A true JPS63302530A (en) 1988-12-09
JP2564487B2 JP2564487B2 (en) 1996-12-18

Family

ID=15205861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62137746A Expired - Lifetime JP2564487B2 (en) 1987-06-02 1987-06-02 Circuit board and hybrid integrated circuit thereof

Country Status (1)

Country Link
JP (1) JP2564487B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004014896A (en) * 2002-06-10 2004-01-15 Fuji Electric Holdings Co Ltd Resin sealed semiconductor device and its manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848432A (en) * 1981-09-17 1983-03-22 Denki Kagaku Kogyo Kk Manufacture of hybrid integrated circuit
JPS58151039A (en) * 1982-03-04 1983-09-08 Denki Kagaku Kogyo Kk Hybrid integrated circuit substrate
JPS622587A (en) * 1985-06-28 1987-01-08 電気化学工業株式会社 Hybryd integrated circuit for high power

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848432A (en) * 1981-09-17 1983-03-22 Denki Kagaku Kogyo Kk Manufacture of hybrid integrated circuit
JPS58151039A (en) * 1982-03-04 1983-09-08 Denki Kagaku Kogyo Kk Hybrid integrated circuit substrate
JPS622587A (en) * 1985-06-28 1987-01-08 電気化学工業株式会社 Hybryd integrated circuit for high power

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004014896A (en) * 2002-06-10 2004-01-15 Fuji Electric Holdings Co Ltd Resin sealed semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JP2564487B2 (en) 1996-12-18

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