JPS6329956A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6329956A JPS6329956A JP17448186A JP17448186A JPS6329956A JP S6329956 A JPS6329956 A JP S6329956A JP 17448186 A JP17448186 A JP 17448186A JP 17448186 A JP17448186 A JP 17448186A JP S6329956 A JPS6329956 A JP S6329956A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicate glass
- boron
- glass film
- silicate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000005368 silicate glass Substances 0.000 claims abstract description 35
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052796 boron Inorganic materials 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000011521 glass Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 abstract description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 3
- 238000007493 shaping process Methods 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000009499 grossing Methods 0.000 description 5
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 229910015845 BBr3 Inorganic materials 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000005243 fluidization Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- SDKPSXWGRWWLKR-UHFFFAOYSA-M sodium;9,10-dioxoanthracene-1-sulfonate Chemical compound [Na+].O=C1C2=CC=CC=C2C(=O)C2=C1C=CC=C2S(=O)(=O)[O-] SDKPSXWGRWWLKR-UHFFFAOYSA-M 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に、半導体装
置表面の平滑性に優れたシリケートガラス膜の形成方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a silicate glass film with excellent smoothness on the surface of a semiconductor device.
半導体装置は通常、単結晶半導体、多結晶半導体、絶縁
膜等を構成要素として構成され、これらの構成要素は半
導体装置の製造過程において微細加工さｎ１各々の構成
要素の寸法や加工の程度が反映さｎた凹凸が半導体基板
の一主面上に形成でｎ、る。一般にこのような凹凸は半
導体装置製造上好ましくなく、次工程以後の半導体装置
の加工を困難にする。特に、層間絶縁膜の形成工程にお
いてこの凹凸が激しくなり、この凹凸により次工程の金
塩配線工程において、金属配線の断線や短絡を引き起こ
し、製造上の良品率の低下、および半導体装置の信頌性
の低下をきたす。Semiconductor devices are usually composed of components such as single crystal semiconductors, polycrystalline semiconductors, and insulating films, and these components are microfabricated during the manufacturing process of the semiconductor device, and the dimensions and degree of processing of each component are reflected. Concave and convex portions are formed on one principal surface of the semiconductor substrate. In general, such unevenness is unfavorable in the manufacturing of semiconductor devices, and makes it difficult to process the semiconductor device in subsequent steps. In particular, this unevenness becomes severe in the process of forming an interlayer insulating film, and this unevenness causes disconnection or short-circuiting of metal wiring in the next gold salt wiring process, resulting in a decrease in the quality of products in manufacturing and an issue with the reliability of semiconductor devices. It causes a decline in sexuality.
従来は、このような凹凸を平滑化するために、まず化学
気相堆積法によって例えば、８重ｔ％のリンシリケート
ガラス膜（以下ＰＳＧ膜と略記する）ｔ−この凹凸のあ
る構造上に堆積しｔ後、引き続いて塩層１０００℃、ｇ
累（Ｎｚ ）または水蒸気（Ｈ鵞Ｕ）雰囲気にて熱処ｉ
を行なうことにより、ＰＳＧ膜を流動化せしめ、表面の
凹凸を平滑化きせるという方法をとっていた。Conventionally, in order to smooth out such unevenness, first, a chemical vapor deposition method is used to deposit, for example, an 8% phosphorus silicate glass film (hereinafter abbreviated as PSG film) on the uneven structure. After that, the salt layer was heated at 1000℃, g
Heat treatment in a cumulative (Nz) or steam (H) atmosphere
By doing this, the PSG film was fluidized and surface irregularities were smoothed.
ところで半導体装置の高渠積化、高機能化に伴ない、半
導体装置？構成する半導体素子の接合深での浅薄化が必
要となる。このためには半導体素子形成後の熱処理の低
温化が不可欠でアリ、上述しｙｔ Ｐ Ｓ Ｇ膜の平滑
化工程においても、例えば９００°Ｃ以下の熱処理温度
の低温化が必須である。By the way, as semiconductor devices become more integrated and more sophisticated, semiconductor devices? It is necessary to reduce the junction depth of the constituent semiconductor elements. For this purpose, it is essential to lower the temperature of the heat treatment after forming the semiconductor element, and in the smoothing process of the ytPSG film mentioned above, it is also essential to lower the heat treatment temperature to, for example, 900° C. or less.
しかしながら、上述し友従来のＰＳＧ膜の平滑化工程に
おいては、熱処理温度を９００℃以下にする定めには、
ＰＳＧ膜のリン装置を１３重量％以上にまで高める必要
があっ友。このリン譲度１３重ｔ％以上のＰＳＧ膜は、
吸湿性が大きく配線材料として多用されているアルミニ
ウムを腐食し、半導体装置の信頓性を著しく劣化させる
という重大な欠点があっｔｏ
〔問題点を解決する念めの手段〕
本発明の半導体装置の製造方法は、半導体基板の一主面
上に７リケートガラス膜を形成する工程と、前記基板を
ボロン金倉む雰囲気で熱処理して前記シリケートガラス
膜の表面にボロンを含有するシリケートガラス膜を形成
する工程と、前記シリケートガラス膜に対して所定の選
択比を有するエツチング法を用いて前記ボロンを含有す
るシリケート膜と全てエツチング除去する工程を含むこ
とを特徴とする。However, in the conventional PSG film smoothing process mentioned above, the heat treatment temperature is set to be 900°C or less.
It is necessary to increase the phosphorus content of the PSG film to 13% by weight or more. This PSG film with a phosphorus yield of 13 fold t% or more is
There is a serious drawback that aluminum, which is highly hygroscopic and is often used as a wiring material, is corroded and the reliability of the semiconductor device is significantly deteriorated. The manufacturing method includes the steps of forming a 7-silicate glass film on one main surface of a semiconductor substrate, and heat-treating the substrate in an atmosphere containing boron to form a silicate glass film containing boron on the surface of the silicate glass film. and a step of completely etching away the boron-containing silicate film using an etching method having a predetermined selectivity with respect to the silicate glass film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
ある。be.
第１図（ａｌにおいて、１１は半導体基板、１２はゲー
ト酸化膜、１３は多結晶シリコン配線、１４はＩｉ間間
融縁膜して使用されるＰＳＧ膜である。In FIG. 1 (al), 11 is a semiconductor substrate, 12 is a gate oxide film, 13 is a polycrystalline silicon wiring, and 14 is a PSG film used as a fusion film between Ii.
本尖施例においてはンリケートガラス膜トＬｆＳＧ膜を
用いた。ＰＥＧ膜１膜上４化学気相堆積法によって８重
ｉ％のＰＳＧｉ堆積している。堆積後のＰＳＧ膜１４は
凹凸が甚しく、次工程の金属配線において断線や短絡等
の問題を生じる。ＰＥＧ膜１膜上４面の凹凸の平滑化の
方法として、まず、ボロン（Ｂｌを含む雰囲気において
熱処理を行なう。In the present embodiment, a hydrated glass film and an LfSG film were used. 8x i% PSGi was deposited on one PEG film by chemical vapor deposition. The PSG film 14 after deposition is extremely uneven, causing problems such as disconnections and short circuits in metal wiring in the next process. As a method for smoothing the unevenness on the four upper surfaces of the PEG film 1, heat treatment is first performed in an atmosphere containing boron (Bl).
通し７ｔ’Ｊ累ガス３１／ｍｉｎ、水蒸気（ＨｚＯ）
中を通した酸素ガス１１／ｍｉｎを導入する。この熱
処理によってＰ ８ Ｇ膜１４の表面にはボロン（Ｂｌ
が拡散さｒ９、第１図（ｂｌに示すように、ボロンリン
シリケートガラス（以下ＢＰＳＧと略記する）膜１５が
形成される。このＢＰＳＧ 膜は脱甲に含有ざ詐るボ
ロン濃度が高く、容易に流動化するので、９００℃とい
う比較的低温においても十分に流動化する。この結果、
凸部１６表面のＢＰＳＧは凹部１７表面に移動し、ＢＰ
ＳＧ膜１５の表面は平滑になる。こｎと同時に、９００
’Ｏにおいて普化している８重ｔチのＰＥＧ膜１膜上４
上層のＢｆ’ＳＧ膜１５の膜性５流動化？容易化し＃、
動化するため、凹部１７におけるＰＳＧ膜１４■界面平
滑性は改善でれる。半導体基板表面に形成でれたＨＰＳ
ＧＩＩ・し
１５は吸湿群が大さいため、引ききいてこのＢＰＳＧ膜
１５をエツチング除去する。このエツチングの際、弗化
水素酸（■゛）を含む液体をエツチング液として使用す
る。ＢＰＳＧ膜１５のエツチング速度はＰＳＧ膜１４の
３分の１８度と小さくできるため、凹部１７においては
、ＢＰＳＧ膜厚が厚いこトド相１ってＰＳＧ膜１４のエ
ツチング量が小石く、一方凸部１６においてはＢＰＳＧ
膜厚が薄いこトｌｌｌまってＰＳＧＪａ１４のエツチン
グ量が大きくなる。この結果、第１図（Ｃ）に示すよう
に、ＢＰＳＧ膜１５除去後のＰＳＧ膜１４の表面凹凸形
状は一層改善される。7t'J total gas 31/min, water vapor (HzO)
Oxygen gas passed through the tube at a rate of 11/min is introduced. Through this heat treatment, boron (Bl) is formed on the surface of the P 8 G film 14.
is diffused, and as shown in FIG. 1 (bl), a boron phosphorus silicate glass (BPSG) film 15 is formed. It fluidizes sufficiently even at a relatively low temperature of 900°C.As a result,
The BPSG on the surface of the convex portion 16 moves to the surface of the concave portion 17, and the BPSG
The surface of the SG film 15 becomes smooth. At the same time as this, 900
8-fold PEG film 1 film 4 on
Membrane quality 5 Fluidization of the upper layer Bf'SG film 15? Facilitate#,
As a result, the smoothness of the interface between the PSG film 14 and the concave portion 17 can be improved. HPS formed on the surface of a semiconductor substrate
Since the GII film 15 has a large moisture absorption group, the BPSG film 15 is removed by etching. During this etching, a liquid containing hydrofluoric acid (■) is used as an etching solution. Since the etching speed of the BPSG film 15 can be reduced to 18 degrees, which is 1/3 of that of the PSG film 14, in the concave portions 17, the amount of etching of the PSG film 14 is small in the case of the thicker BPSG film. BPSG in 16
As the film thickness becomes thinner, the amount of etching of PSGJa14 increases. As a result, as shown in FIG. 1C, the surface unevenness of the PSG film 14 after the removal of the BPSG film 15 is further improved.
なお、熱処理を行なう以前のＰＳＧ膜１４の凹凸形状に
よっては、凹部１８に形成場れ７ｔＢＰＳＧ膜１５の膜
厚が凸部１６に形成され＊ＢＰＳＧ膜１５の膜厚５比較
して数倍になる場合がある。この場合には、弗化水素酸
（ＨＦ）ｆ、含む液体のみで、ＢＰＳＧ膜１５ｆｔエツ
チング除去すると、エツチング前に凹部であったものが
凸部になるなど形状の不都合音生じる。この場合には、
ＣＦ４ガスを用いたドライエツチング金使用するとＢＰ
ＳＧのエッチング速度がＰＳＧのエツチング速肛と比較
して２倍程度に制御できるので、このエツチング法を併
用することによりＢＰＳＧ膜１５エツチング後のＰＳＧ
膜１４の表面凹凸形状の平滑化を最適化することができ
る。Note that depending on the uneven shape of the PSG film 14 before heat treatment, the thickness of the BPSG film 15 formed in the concave portions 18 will be several times that of the convex portions 16. There are cases. In this case, if 15 feet of the BPSG film is removed by etching only with a liquid containing hydrofluoric acid (HF), an undesirable shape will occur, such as concave portions before etching becoming convex portions. In this case,
BP when using dry etching gold using CF4 gas
Since the etching speed of SG can be controlled to be about twice that of PSG, by using this etching method in combination, the PSG after etching of the BPSG film 15 can be controlled.
The smoothing of the surface unevenness of the film 14 can be optimized.
以上の工程を経て残っ７２：ＰＳＧｌ１１４のリン濃度
は８重ｔチであり、且つボロン（ａを含まないため、吸
湿性は無く信頼性が良好である。After the above steps, the remaining 72:PSGl114 has a phosphorus concentration of 8x, and does not contain boron (a), so it has no hygroscopicity and has good reliability.
以上詳細に述べ友ように、本実施例においては、従来１
０００℃の高温熱処理を必要としていた層間ＰＳＧ膜の
表面平滑化が９００℃という比較的低温な熱処理で１」
能であり、半導体装置の高集積化および高機能化が実現
できるという大きな利点を有する。As described in detail above, in this embodiment, conventional 1
The surface smoothing of the interlayer PSG film, which previously required high-temperature heat treatment at 900 degrees Celsius, has now been achieved with relatively low-temperature heat treatment at 900 degrees Celsius.
It has the great advantage of realizing higher integration and higher functionality of semiconductor devices.
第２図（ａｌ〜（Ｃ１は本発明の第２の実施例の工程順
縦断面図であシ、ＭＯ８型半導体装置の眉間絶縁膜とし
て、リン（ＰＩ等の不純物を含まないシリケートガラス
（以下５ｉ０２と略記する）膜を用いた場合を示し友も
のである。FIG. 2 (al~(C1 is a longitudinal cross-sectional view in the order of steps of the second embodiment of the present invention), in which a silicate glass (hereinafter referred to as 5i02) is used.
第２図（ａ）において、２１は半導体基板、２２はゲー
ト酸化膜、２３は多結晶シリコン配線、２４はＳ ｉｏ
２膜である。従来の窒素（Ｎ２ ）雰囲気中での熱処
理においては、５ｉ０２膜２４０表面凹凸を平滑化する
ことは困難であり、次工程の金属配線工程にて加工上の
困難を有していたが、本発明を用いることにより、５ｉ
（Ｊ２膜２４の凹凸表面の平滑化が可；泪となる。In FIG. 2(a), 21 is a semiconductor substrate, 22 is a gate oxide film, 23 is a polycrystalline silicon wiring, and 24 is an Sio
There are two membranes. In the conventional heat treatment in a nitrogen (N2) atmosphere, it was difficult to smooth the surface unevenness of the 5i02 film 240, which caused processing difficulties in the next metal wiring process. By using 5i
(The uneven surface of the J2 film 24 can be smoothed.
前述した第１の実施例と同様に、半導体基板２１を例え
ば、温度９００℃の炉に保持し、炉内に三臭化ボロン（
ＢＢｒ３）を通した窒素（Ｎ２）ガス３１膜ｍ ｉロ
および酸素（Ｏ２）ガス１１膜ｍ ｉ ｎ ｆｃ導入す
る。Similarly to the first embodiment described above, the semiconductor substrate 21 is held in a furnace at a temperature of 900° C., and boron tribromide (
Nitrogen (N2) gas through 31 membranes (BBr3)
and 11 films of oxygen (O2) gas are introduced.
この熱処理により、第２図（ｂｌに示すごとく、５ｉ０
２２４の表面にはボロ／（Ｂ）が拡散され、ボロン７リ
ケートガラス（以下ＢＳＧと略記する）膜２５が形成さ
れ、且つこのＢＳＧ膜２５は流動して表面が平滑化され
る。引きαいて、例えば弗化水素酸（ＨＦ ）の５倍希
釈水溶液にようでＢＰＧ膜２５にエツチング除去する。By this heat treatment, as shown in Fig. 2 (bl), 5i0
Boro/(B) is diffused onto the surface of the substrate 224 to form a boron 7 silicate glass (hereinafter abbreviated as BSG) film 25, and this BSG film 25 flows to smooth the surface. Then, the BPG film 25 is etched away using, for example, a 5-fold diluted aqueous solution of hydrofluoric acid (HF).
前述し几第１の実施列と同様に、ＢＳＧのエツチング速
度が５ｉ（Ｊ２のエツチング速度よシ小さいことに起因
して、エツチング後の８ｉ０２膜２４の表面は第２図（
Ｃ）に示技術においては実現できなかつ２４ＩＳｉ０２
膜の表面の平滑化が９００°Ｃという比較的低温に
おいて可能であり、半導体装置の８集積化、および高信
頼性化が実現できるという大きな利点を有する。Similar to the first implementation column described above, the surface of the 8i02 film 24 after etching is as shown in FIG.
C) cannot be realized with the technology shown in 24ISi02
It has the great advantage that the surface of the film can be smoothed at a relatively low temperature of 900° C., and that it is possible to realize 8-integration and high reliability of semiconductor devices.
また、上述した２つの実施例においては、シリケートガ
ラス膜の堆積工程、ボロン２含む雰囲気中での熱処理工
程およびエツチング工程をそれぞｎ１回のみ行なったが
、２回以上ｍｂ返して行なっても艮い。In addition, in the two embodiments described above, the silicate glass film deposition step, the heat treatment step in an atmosphere containing boron 2, and the etching step were each performed only n times, but even if the steps were repeated two or more times, there was no difference. stomach.
１几、実施例ではシリケートガラスとしてリン金倉むシ
リケートガラスまたは不純物を含まないシリケートガラ
スを使用したが、本発明はこｊ、ら以外にも、ボロン（
Ｂ］、ゲルマニウム（Ｇｅ）、ヒ素（Ａｓ）、アンチモ
ン（Ｓｂ）ｔ−含むシリケートガラス或いはこれらの混
合物を使用することも可能である。In the Examples, phosphorous silicate glass or silicate glass containing no impurities was used as the silicate glass, but in addition to these, boron (
It is also possible to use silicate glasses containing B], germanium (Ge), arsenic (As), antimony (Sb), or mixtures thereof.
さらに、本発明は、ＭＯ８型半導体装置以外にも、バイ
ポーラ型半導体装置、あるいはその他生導体装置一般に
対しても実施することができる。Furthermore, the present invention can be implemented not only for MO8 type semiconductor devices but also for bipolar type semiconductor devices or other general live conductor devices.
以上説１明したように本発明は、シリケートガラス膜を
ボロン（Ｂ）？含む雰囲気中にて熱処理を行なって、シ
リケートガラス膜の表面に流動性の高いボロンを含むシ
リケートガラス膜を形成することにより、半導体装置の
表面が低温で平滑化さｎると共に、ボロンを含むシリケ
ートガラス膜と７リケートガラス膜との界面の平滑化が
促進さｎる。As explained above, in the present invention, a silicate glass film is made of boron (B)? By performing heat treatment in an atmosphere containing boron to form a highly fluid silicate glass film containing boron on the surface of the silicate glass film, the surface of the semiconductor device is smoothed at a low temperature, and the silicate containing boron is Smoothening of the interface between the glass film and the 7-silicate glass film is promoted.
続いて、ボロンを含むシリケートガラス膜と７リケート
ガラス膜とのエツチング速度比が所定の条件で両者をエ
ツチング除去することにより、半導体装置の表面をさら
に平滑化するものである。そして、このエツチングの際
、シリケートガラス膜表面の吸湿性の高いボロンを含む
ノリケートガラス膜は全てエツチング除去するので、信
頼性の高い絶な膜が形成できる。よって、高信頼性・高
集積度の半導体装置が実現できるという効果がある。Subsequently, the surface of the semiconductor device is further smoothed by etching and removing both the boron-containing silicate glass film and the 7-silicate glass film under a predetermined etching rate ratio. During this etching, all of the silicate glass film containing highly hygroscopic boron on the surface of the silicate glass film is etched away, so that a highly reliable and continuous film can be formed. Therefore, there is an effect that a highly reliable and highly integrated semiconductor device can be realized.
第１図＋ａｌ〜（Ｃ１は本発明の第１の実施例の工程順
縦断面図、第２図（ａｌ〜（Ｃ）は本発明の第２の実施
例の工程順縦断面図である。
１１ 、２１・・・・・・半導体基板、１２．２２・・
・・・・ゲート酸化膜、１３．２３・・・・・・多結晶
シリコン配線、１４・・・・・・リンシリケートガラス
膜、２４・・・・・・シリケートガラス膜、１５・・・
・・・ボロンリンシリケートガラス膜、２５・・・・・
・ボロンシリケートガラス膜、１６・・・・・・凸部、
１７．１８・・・・・・凹部。
代理人 弁理士 内 原 晋１、 ・ン第 １
図FIG. 1+al~(C1 is a longitudinal cross-sectional view in the order of steps of the first embodiment of the present invention, and FIG. 2(C) is a longitudinal cross-sectional view in the order of steps of the second embodiment of the present invention. 11, 21... semiconductor substrate, 12.22...
... Gate oxide film, 13.23 ... Polycrystalline silicon wiring, 14 ... Phosphorsilicate glass film, 24 ... Silicate glass film, 15 ...
...Boron phosphorus silicate glass membrane, 25...
・Boron silicate glass film, 16... Convex portion,
17.18... Concavity. Agent: Patent Attorney Susumu Uchihara 1st, ・N 1st
figure
Claims (1)
る工程と、前記基板をボロンを含む雰囲気で熱処理して
前記シリケートガラス膜の表面にボロンを含有するシリ
ケートガラス膜を形成する工程と、前記シリケートガラ
ス膜に対して所定の選択比を有するエッチング法を用い
て前記ボロンを含有するシリケート膜を全てエッチング
除去する工程を含むことを特徴とする半導体装置の製造
方法。a step of forming a silicate glass film on one main surface of a semiconductor substrate; a step of heat-treating the substrate in an atmosphere containing boron to form a silicate glass film containing boron on the surface of the silicate glass film; A method for manufacturing a semiconductor device, comprising the step of etching away all of the boron-containing silicate film using an etching method having a predetermined selectivity with respect to the glass film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61174481A JPH0744216B2 (en) | 1986-07-23 | 1986-07-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61174481A JPH0744216B2 (en) | 1986-07-23 | 1986-07-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6329956A true JPS6329956A (en) | 1988-02-08 |
| JPH0744216B2 JPH0744216B2 (en) | 1995-05-15 |
Family
ID=15979234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61174481A Expired - Lifetime JPH0744216B2 (en) | 1986-07-23 | 1986-07-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744216B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0737886A (en) * | 1993-07-19 | 1995-02-07 | Nec Corp | Manufacture of semiconductor device |
| JP2007165774A (en) * | 2005-12-16 | 2007-06-28 | Mitsubishi Electric Corp | Thin-film laminated substrate, manufacturing method therefor and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59127851A (en) * | 1983-01-11 | 1984-07-23 | Nec Corp | Manufacture of semiconductor device |
| JPS6031241A (en) * | 1983-08-01 | 1985-02-18 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1986
- 1986-07-23 JP JP61174481A patent/JPH0744216B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59127851A (en) * | 1983-01-11 | 1984-07-23 | Nec Corp | Manufacture of semiconductor device |
| JPS6031241A (en) * | 1983-08-01 | 1985-02-18 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0737886A (en) * | 1993-07-19 | 1995-02-07 | Nec Corp | Manufacture of semiconductor device |
| JP2007165774A (en) * | 2005-12-16 | 2007-06-28 | Mitsubishi Electric Corp | Thin-film laminated substrate, manufacturing method therefor and display device |
| JP4684877B2 (en) * | 2005-12-16 | 2011-05-18 | 三菱電機株式会社 | Thin film laminated substrate, manufacturing method thereof, and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0744216B2 (en) | 1995-05-15 |
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