JPH01138736A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the photoetching process of upper wiring layer by enabling an interlayer insulating film to be flattened by a method wherein a BPSG film is deposited on the first wiring layer formed on the surface of a semiconductor substrate and then phosphorus is diffused on overall surface of a PSG film in high concentration formed on the surface of the BPSG film to substitute the BPSG film on the wiring layer successively for the PSG film. CONSTITUTION:A BPSG film 3 is deposited on the first wiring layer 2 formed on a substrate 1 and then a PSG film 6 in high concentration is grown on the surface of the BPSG film 3. Next, phosphorus is diffused on overall surface so that the PSG film in high concentration may be fluidized to be concentrated in lower parts forming thick layers. The BPSG film 3 at the swelled part on the first wiring layer 2 is successively substituted for the PSG film 6 in proportion to the process of phosphorus diffusion to form an interlayer insulating film composed of the two layer structure comprising the fluidized BPSG film 3 and the fluidized PSG film 6. Consequently, when the second wiring layer is formed, the interlayer insulating film thus formed is flattened enabling the photoetching process to be performed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a glabellar insulating film with extremely good flatness.

[Conventional technology]

BACKGROUND ART Recently, BPSG films have been widely used as interlayer insulating film materials for manufacturing semiconductor integrated circuit devices because they can be heated at low temperatures. However, when trying to obtain a semiconductor integrated circuit device with an even finer structure, the flow of the BPSG film becomes gentler, but the high surface tension of the BPSG film itself causes it to become thicker at the higher parts. Therefore, a glabellar insulating film having a relatively angular shape is likely to be formed.

FIGS. 3 and 4 are cross-sectional views of a semiconductor integrated circuit device, each showing the shape of an interlayer insulating film formed by a conventional manufacturing method. That is, FIG. 3 shows a case where a first wiring layer 2 made of a polycrystalline silicon film having a thickness of about 0.7 μm and a width of about 1 μm is formed on a semiconductor substrate 1. However, BPSG with a thickness of about 0.5 μm
When the film 3 is deposited on the first wiring layer 2 by the CVD method and subjected to heat treatment at a temperature of about 900'C, the upper part of the first wiring layer 2 rises and has a steep slope. In order to solve this problem, a PSG film was deposited on the entire surface, and PSGi4 was further diffused to form a fluidized PSGi4, resulting in the structure shown in FIG. According to this method, the shape of the interlayer insulating film becomes more flat, but in this case,
BPSG film on the surface and B with completely different composition from PSG film
A non-fluid body consisting of PO-based substances 5 is formed. This substance is said to be a reaction product of phosphorus (P) and the BPSG film formed during the phosphorus (P) diffusion process, but it is not preferable because it creates irregularities on the surface of the glabella insulating film.

[Problem that the invention seeks to solve]

As described above, the conventional manufacturing method cannot form a flatter interlayer insulating film, which poses a serious problem in the formation of the second and subsequent wiring layers. This problem has increasingly important implications for the manufacture of semiconductor integrated circuit devices in the era of submicron wiring layer widths.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a method for manufacturing a semiconductor device including an interlayer insulating film forming step that can extremely effectively flatten steps in wiring layers having submicron line widths.

[Means for solving problems]

According to the present invention, a method for manufacturing a semiconductor device includes a step of forming a first wiring layer on a surface of a semiconductor substrate, a step of depositing a BPSG film on the first wiring layer, and a step of depositing a BPSG film on the first wiring layer.
A heat treatment step for fluidizing the SG film and the fluidized B
forming a high concentration PSG film on the PSG film; and diffusing phosphorus over the entire surface of the high concentration PSG film and sequentially replacing BPSGIli on the first wiring layer with the PSG film. and a step of forming a glabellar insulating film.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) and 1(b) are process diagrams for forming an insulating film between the eyebrows, showing an embodiment of the present invention.

According to this embodiment, a first wiring layer 2 made of a polycrystalline silicon film with a thickness of about 0.7 μm and a width of about 1 μm is formed on a semiconductor substrate 1, as in the conventional method, and then A BPSG film 3 having a thickness of about 0.5 μm is grown by CVD and then flowed by heat treatment. It is better to perform this heat treatment in a steam atmosphere, and the BPSG
It is also effective for stabilizing boron (B) in the film. Thereafter, a length of PSGSeO2 with a high concentration (for example, 12 mol % phosphorus concentration) of approximately 0.3 μm in thickness is formed using the CVD method. [
See Figure 1(a)].

Thereafter, by diffusing phosphorus (P) over the entire surface, the highly concentrated PSGWA 6 is fluidized and guided to thickly gather at low points. At this time, as the phosphorus (P) diffusion progresses, the BPSG film 3 in the raised portions on the first wiring layer 2 is sequentially replaced by the PSG film 6, resulting in a very flat surface as a whole.
That is, the fluidized BPSG film 3 and the fluidized PSGSe
A glabellar insulating film having an O2 layer structure can be obtained [see FIG. 1(b)].

Therefore, when forming the second wiring layer, the obtained glabellar insulating film is so flat that photoetching can be carried out without any problem.

FIGS. 2(a) to 2(c) are process diagrams for forming an interlayer insulating film showing another embodiment of the present invention. According to this embodiment, a high concentration of PSGSeO2 is formed on the surface of the BPSG film 3 deposited on the surface of the semiconductor substrate 1, as in the previous embodiment. Next, the oxide film covering the back surface of the semiconductor substrate 1 is removed to expose the back surface (see FIG. 2(a)).

Thereafter, an interlayer insulating film consisting of a fluidized BPSG film 3 and a fluidized high-concentration PSGSeO2 layer structure is formed by diffusion of phosphorus (P) over the entire surface using the same method as in the previous embodiment.

At this time, phosphorus (P) is also diffused on the back surface at the same time, and a phosphorus diffusion layer 7 and a PSG layer obtained by phosphorus diffusion are formed on the back surface.
A film 8 is formed respectively (see FIG. 2(b)).

This phosphorus diffusion to the back surface is for zero gettering due to phosphorus (P), and is effective in reducing leakage current of the semiconductor device.

Thereafter, the PSG film 8 obtained by phosphorus diffusion on the back surface and the high concentration PSG film 6 on the front surface are removed using, for example, a hydrofluoric acid buffer solution.

[See Figure 2(c)].

Since the high concentration PSGM 6 and the BPSG film 3 have different etching rates, if the time is set appropriately, the BPSG film 3 can be left in a fluidized form without being etched much.

Further, even if batch type isotropic plasma etching is used, the difference in etching rate can be utilized, so that only the PSG film can be easily etched away without requiring strict control. The shape of the glabellar insulating film thus obtained is not only flatter than the original single-layer BPSG film, but also a structure capable of reducing leakage current is simultaneously realized.

〔Effect of the invention〕

As described in detail above, according to the present invention, the interlayer insulating film can be further planarized without using particularly expensive equipment, so that photoetching of the upper wiring layer can be easily performed. The effect is particularly significant when applied to the manufacture of semiconductor integrated circuit devices in the era of submicron wiring widths.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are process diagrams for forming an interlayer insulating film showing one embodiment of the present invention, and FIGS. 2(a) to (c) are interlayer insulating films showing another embodiment of the present invention. FIGS. 3 and 4 are cross-sectional views of a semiconductor integrated circuit device showing the shape of an interlayer insulating film formed by a conventional manufacturing method, respectively. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First wiring layer, 3...
...BPSG film, 6... High concentration PSG film, 7...
Phosphorus diffusion layer on the back surface, 8... PSG film obtained by diffusion of phosphorus on the back surface.

Claims (1)

[Claims] a step of forming a first wiring layer on the surface of the semiconductor substrate; a step of depositing a BPSG film on the first wiring layer; a heat treatment step of fluidizing the BPSG film; forming a highly concentrated PSG film on the BPSG film; and diffusing phosphorus over the entire surface of the highly concentrated PSG film and sequentially replacing the BPSG film on the first wiring layer with a PSG film. 1. A method of manufacturing a semiconductor device, comprising a step of forming an interlayer insulating film including a step of flattening the film.