JPS63308350A - Formation of insulating layer - Google Patents

Abstract

PURPOSE:To prevent the occurrence of voids due to air bubbles trapped in an insulating layer in the fine gaps between wirings by performing a heat treatment (reflow process) for planarizing the surface of the interlayer insulating layer in a high-pressure helium atmosphere. CONSTITUTION:To a high-pressure vessel 1 made of stainless steel, a gas introducing pipe 2 and a gas exhaust pipe 3 are connected respectively through a cut-off valve 4 and a pressure regulator valve 5, and a semiconductor substrate 6 received in a holder 7 is placed in the center of the high-pressure vessel 1. On the surface of the semiconductor substrate 6, a film to be subjected to a planarization heat treatment is formed which is made of phosphosilicate glass or the like, and around the holder 7, a heater 8 is provided for heating the semiconductor substrate 6. And the glass layer of the phosohosilicate or borophosphosilicate system produced on the semiconductor chip surface having a plurality of wirings arranged at fine intervals is heated in a high-pressure atmosphere so as to reflow. With this, the occurrence of voids in the insulating layer consisting of the phosphosilicate or borophosphosilicate system glass layer in the gaps between the wirings is prevented.

Description

[Detailed Description of the Invention] [Summary] When forming a glabellar insulating layer on the surface of a semiconductor device chip on which a plurality of wiring lines arranged at minute intervals are formed, heat treatment is performed to flatten the surface of the interlayer insulating layer. (Reflow treatment) is performed in a high-pressure helium atmosphere to prevent the generation of voids due to air bubbles trapped in the insulating layer in minute gaps between interconnects.

[Industrial application field]

The present invention relates to a glabella insulating layer in a semiconductor device.

In particular, it relates to a heat treatment method for planarizing the surface of an interlayer insulating layer.

[Conventional technology]

Multilayer wiring is used in many semiconductor devices. As the glabellar insulating layer in this multilayer wiring structure, a film of silicate phosphoric acid glass (PSG) or borosilicate phosphoric acid glass (BPSG), which melts at a lower temperature than PSG, is mainly used.

These PSG and BPSG films are usually formed on a semiconductor device substrate at a relatively low temperature of about 400° C. by chemical vapor deposition (CVD'). The surface of a PSG film, etc., formed by CVD is not flat due to unevenness caused by the underlying wiring, etc., and if an upper wiring layer is formed on top of this, problems such as disconnection or poor conduction may occur at one level difference. is likely to occur. For this purpose, after forming these films such as PSG, the semiconductor device substrate is heat-treated at a temperature such that the films such as PSG exhibit fluidity, and the surface of the insulating layer between the eyebrows such as PSG is flattened. is being carried out. This heat treatment has conventionally been performed in nitrogen gas.

[Problem that the invention seeks to solve]

However, with the miniaturization of semiconductor devices, voids are becoming more likely to occur in the glabella insulating layer.

FIG. 2 shows a cross section of the glabella insulating layer 21, the semiconductor substrate 22 and the wiring 23 thereunder, in which the voids 20 as described above have occurred. The wiring 23 is made of a heat-resistant material such as polysilicon. As shown in the figure, the width and height of the two wires 230 are about 1 μm, and the gap between the wires 23 is 0.8 to 1 μm. in this way.

The void 20 is a PSG that fills the gap between the interconnects 23
It occurs in an insulating layer made up of such materials, and the smaller the distance between wires, the more likely it is to occur, and it does not occur when the distance between wires becomes large to a certain extent.

As mentioned above, the reason why voids are more likely to occur between wiring lines as the distance becomes smaller is considered to be as follows. That is, the glabellar insulating layer immediately after being formed on the semiconductor substrate by CVD has a cross-sectional shape as shown in the schematic diagram of FIG. As shown.

PSG or BPSG film 24 in the as-deposited state
teeth.

The wires 23 are thick in the lateral direction near their heads, but are relatively thin between the wires 23, and as a result, a wide space exists deep between the wires 23. When such a film 24 such as PSG is heat-treated and melted, the films 24 such as PSG formed on the heads of adjacent wirings 23 are first fused together, and the large space below them is melted. Gas (previously nitrogen)
will be trapped. In this way, the atmospheric gas during the hydrochlorination heat treatment remains in the glabellar insulating layer as voids.

The above-mentioned voids may be exposed to the outside air when a film such as PSG above them is removed during an etching process or the like to form a contact hole in the glabella insulating layer.

In other words, it is not a space confined within the glabellar insulating layer, but a hole formed in the N-glabellar insulating layer. Such a hole becomes a step when upper layer wiring is formed on top of it, causing disconnection or poor conduction.Also, the processing agent used in the etching remains, and the hole is formed on the insulating layer between the eyebrows. There were inconveniences such as corroding the wires and causing disconnections.

[Means for solving problems]

What are the problems with the above-mentioned conventional glabella insulating layer formation?

By heating and reflowing a silicate-based or borosilicate-based glass layer produced on the surface of a semiconductor device chip having a plurality of interconnections arranged at minute intervals in a high-pressure helium atmosphere, The problem is solved by the method for forming an insulating layer according to the present invention, which is characterized in that voids are prevented from forming in the insulating layer made of the silicate-phosphate or borosilicate-phosphate glass layer.

[Effect]

By performing the flattening heat treatment of the glabellar insulating layer made of PSG or BPSG in a high-pressure helium atmosphere, no voids are generated in the flattened glabellar insulating layer.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing the configuration of a heat treatment apparatus used in the present invention. A gas inlet pipe 2 and a gas discharge pipe 3 are connected to a high pressure vessel 1 made of stainless steel, for example, via a shutoff valve 4 and a pressure regulating pulp 5, respectively. A semiconductor substrate 6 housed in a holder 7 is placed in the middle of the high-pressure container 1 . On the surface of the semiconductor substrate 6, a film (not shown) made of PSG or the like and subjected to planarization heat treatment is formed. A heater 8 is provided around the holder 7 to heat the semiconductor substrate 6 to about 900 to 1000°C.

A helium cylinder (not shown) is connected to the gas introduction pipe 2 , and helium gas is introduced into the high-pressure vessel 1 through the shutoff valve 4 . After the inside of the high pressure vessel 1 has been sufficiently replaced with helium gas.

Close the shutoff valve 4. A current is passed through the heater 8 to heat the semiconductor substrate 6. The pressure inside the high-pressure container 1 is regulated to a predetermined pressure by a pressure regulating valve 5.

In this case, a small amount of helium may be allowed to flow without completely closing the shutoff valve 4.

As described above, when the nine interlayer insulating layers are made of PSG, they are heated at 950 DEG C. to 1050 DEG C. for about 30 minutes, and when they are made of BPSG, they are heated at about 900 DEG C. for about 30 minutes in a helium atmosphere. Further, the pressure of the helium atmosphere may be 1 atm or more, preferably 10 atm.

FIG. 4 is a schematic diagram showing a cross section of the semiconductor substrate 6 heat-treated in a helium atmosphere as described above. A wiring 11 having the same dimensions and structure as explained in FIG. 2 is formed on a semiconductor substrate 6 such as a silicon wafer.
A glabellar insulating layer 12 made of PSG or BPSG is formed between the eyebrows 1 and on the upper surface. The glabellar insulating layer 12, which has been heat-treated in a helium atmosphere for planarization, does not have voids that conventionally occur between adjacent wiring lines.

In the above, heat treatment was performed by introducing nitrogen gas instead of helium gas as in the past, but at a high pressure of 10 atmospheres, but in this case, it was not possible to prevent the generation of voids. Ta.

Note that the present invention is not limited to flattening heat treatment of a glabellar insulating layer in a semiconductor device, but can also be applied to the removal of air bubbles and voids in other materials that have a small amount of helium permeability (both in a molten state).

〔Effect of the invention〕

According to the present invention, the generation of voids in the glabellar insulating layer made of PSG or BPSG provided in a semiconductor device is prevented, and disconnections or conduction defects in wiring caused by voids are reduced, and thereby the semiconductor device This has the effect of improving manufacturing yield and reliability.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the configuration of a heat treatment apparatus used in the present invention. FIG. 2 is a cross-sectional view showing voids occurring in the glabellar insulating layer. FIG. 3 is a schematic diagram showing the cross-sectional shape of the glabellar insulating layer immediately after being formed by CVD. FIG. 4 is a schematic diagram showing a cross section of the glabellar insulating layer heat-treated by the method according to the present invention. In fig. 1 is a high pressure vessel, 2 is a gas introduction pipe. 3 is the gas exhaust pipe, 4 is the shutoff valve. 5 is a pressure control valve, and 6 and 22 are semiconductor substrates. 7 is a holder, 8 is a heater. 11 and 23 are wiring, and 12 and 21 are insulating layers between the eyebrows. 20 is void. 24 is a PSG or BPSG film. ε circle N spear n month (2 m th Jihyaku angle βl reconnaissance) 1
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Claims (1)

[Claims] By heating and reflowing a silicate-based or borosilicate-based glass layer produced on the surface of a semiconductor device chip having a plurality of interconnections arranged at minute intervals in a high-pressure helium atmosphere, A method for forming an insulating layer, which comprises forming an insulating layer made of the silicate-based or borosilicate-based glass layer to prevent the generation of voids.