JPH01272138A - Manufacture of wiring - Google Patents
Manufacture of wiringInfo
- Publication number
- JPH01272138A JPH01272138A JP18934087A JP18934087A JPH01272138A JP H01272138 A JPH01272138 A JP H01272138A JP 18934087 A JP18934087 A JP 18934087A JP 18934087 A JP18934087 A JP 18934087A JP H01272138 A JPH01272138 A JP H01272138A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- insulating film
- substrate
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000137 annealing Methods 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 13
- 238000005275 alloying Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 36
- 239000011229 interlayer Substances 0.000 abstract description 9
- 229910045601 alloy Inorganic materials 0.000 abstract description 5
- 239000000956 alloy Substances 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 230000005012 migration Effects 0.000 abstract description 4
- 238000013508 migration Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 230000008020 evaporation Effects 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 238000005324 grain boundary diffusion Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 241001414890 Delia Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置の配線の製造方法に関する。[Detailed description of the invention] <Industrial application field> The present invention relates to a method of manufacturing wiring for a semiconductor device.
〈従来の技術〉
ＬＳＩのチップサイズを縮小するのに有効な手段として
、Ａｌｌ・Ｓｉの多層配線技術がある。ところが、ＩＭ
目のＡＩ Ｓｉ配線を形成し、該Ａｄ−５ｉ配線上に層
間絶縁膜を形成する際、長時間の熱処理を必要とし、こ
の熱処理工程中にＡｌの縦方向の突起物（ヒロック）が
成長し、層間膜クラック、層間短絡といった半導体装置
の絶縁不良を引き起こすことが多い。<Prior Art> All/Si multilayer wiring technology is an effective means for reducing the chip size of an LSI. However, I.M.
When forming a second AI Si wiring and an interlayer insulating film on the Ad-5i wiring, a long heat treatment is required, and vertical protrusions (hillocks) of Al grow during this heat treatment process. , interlayer film cracks, and interlayer short circuits, which often cause insulation defects in semiconductor devices.
一般にヒロック成長は加熱に々る圧縮圧力を緩和するた
めに生じる局所的な縦方向の結晶成長であると考えられ
ている。結晶成長は粒界拡散によって支配されてｒるた
め、ヒロック成長に粒界拡散が大きく関与していると考
えられる。それ故、Ａｌｌ−３ｉ層形成後にランプアニ
ール法による短時間のブリアニールを行な贋、Ａｌ・Ｓ
ｉの結晶粒を予め成長させて粒界長を短くすることによ
り、その後の熱処理に対して安定でヒロック成長を抑制
できる配線を形成する方法がある。Hillock growth is generally considered to be localized vertical crystal growth that occurs to relieve the compressive pressure caused by heating. Since crystal growth is controlled by grain boundary diffusion, grain boundary diffusion is considered to be largely involved in hillock growth. Therefore, after forming the All-3i layer, short-time briane annealing is performed using the lamp annealing method.
There is a method of forming a wiring that is stable against subsequent heat treatment and can suppress hillock growth by growing the crystal grains of i in advance to shorten the grain boundary length.
一方、ＬＳＩの高集積化に伴い、コンタクト径がより＠
剣になるが、Ａｌ−５ｉのようにＡｌ中にＳｉを含有さ
せた材料を用いる配線はコンタクし、最悪の場合にはコ
ンタクト不良になる。この問題を解決するためにＴ ｉ
ｒ Ｗ ＋或いはＴｉＷをバリアメタルとしてＳｉ基板
とＡｊｌ’−Ｓｉ配線の間に形成し、Ａｌ−５ｉ配線か
らＳｉが流出するのを遮ぎる方法がある。On the other hand, as LSIs become more highly integrated, the contact diameter becomes more
However, wiring using a material containing Si in Al, such as Al-5i, will contact, and in the worst case, it will result in a contact failure. To solve this problem, T i
There is a method of forming r W + or TiW as a barrier metal between the Si substrate and the Ajl'-Si wiring to block Si from flowing out from the Al-5i wiring.
〈発明が解決しようとする問題点〉
上述のプリアニールにより、ＡＡ’−Ｓｉの結晶粒を予
め成長させる方法では結晶粒径を８μｍ以上に成長させ
ないとヒロック成長の抑制効果が現われない。ところが
微細なＡｌ−５ｉ配線においてＡＩ Ｓｉの結晶粒径の
大きいものを用いると、熱ストレスにより断線に到るス
トレスマイグレーション不良が生じ易いという問題があ
る。<Problems to be Solved by the Invention> In the method of pre-growing AA'-Si crystal grains by pre-annealing described above, the effect of suppressing hillock growth does not appear unless the crystal grain size is grown to 8 μm or more. However, if AI Si with a large crystal grain size is used in fine Al-5i wiring, there is a problem in that stress migration failures that lead to disconnection due to thermal stress are likely to occur.
また上述のバリアメタルを形成する方法では、長時間の
熱処理工程において、コンタクト部へのＳｉの析出を抑
えることができ、更にＡ４・Ｓｉ配線からのヒロックの
発生をある程度抑制できるが、ヒロックの抑制はバリア
メタル本来の目的ではないため充分と言えず、デパイヌ
の信頼性に悪影口を及ぼすという問題がある。In addition, in the method of forming barrier metal described above, it is possible to suppress the precipitation of Si on the contact part during the long-time heat treatment process, and furthermore, it is possible to suppress the generation of hillocks from A4/Si wiring to some extent, but the suppression of hillocks is Since this is not the original purpose of barrier metal, it cannot be said to be sufficient, and there is a problem that it has a negative effect on the reliability of Depaine.
〈問題点を解決するための手段〉
本発明は上述する問題点を解決するためになされたもの
で、複数個の素子を形成した半導体基板の主面上にＴｉ
−Ｗ層とＡｌ−９ｉ層とを順次形成し、前記素子間を電
気的に相互接続する配線とハ′
して前記Ｔｉ−Ｗ層とＡｌ１−８上層とをゼターニング
する工程と、前記半導体基板をプリアニールして前記Ａ
ｌ−８上層をＴｉ−Ｗ層と合金化する工程とを有し、ｋ
ｌ−５ｉ −Ｔ ｉ −Ｗの結晶粒径は３μｍ以下で
ある配線の製法を提供するものである。<Means for Solving the Problems> The present invention has been made to solve the above-mentioned problems.
- a step of sequentially forming a W layer and an Al-9i layer, and zeturning the Ti-W layer and the Al1-8 upper layer with wiring for electrically interconnecting the elements; Pre-anneal the substrate and perform the above A
alloying the l-8 upper layer with the Ti-W layer, and k
The present invention provides a method for manufacturing wiring in which the crystal grain size of l-5i-T i -W is 3 μm or less.
また、本発明は上記プリアニールとしてランプアニーｌ
ｔ行なう配線の製法を提供するものである。Further, the present invention also provides lamp annealing as the above-mentioned pre-annealing.
This invention provides a method for manufacturing wiring.
〈作 用〉
上述の如ぐＡＪ−５ｉ層とＳｉ基板との間にバリアメタ
ルとしてＴｉ−Ｗ層を形成し、更にヲンプアニーＩｖを
行なりてＡｌ−５４層中にＴｉ、Ｗ系の合金を混入させ
ることにより、Ｓｉの析出が抑制できる上、配線材料の
結晶粒が３μｍ以下であってもＡ４の粒界拡散が抑制さ
れてヒロック成長を抑制できる。また、結晶粒径が従来
に比べて小さいため、結晶粒径が大きいことによるスト
レスマイグレーション不良を抑制することが可能となる
。<Function> A Ti-W layer is formed as a barrier metal between the AJ-5i layer and the Si substrate as described above, and a wet annealing Iv is further performed to inject Ti and W-based alloys into the Al-54 layer. By mixing Si, precipitation of Si can be suppressed, and even if the crystal grains of the wiring material are 3 μm or less, grain boundary diffusion of A4 can be suppressed and hillock growth can be suppressed. Furthermore, since the crystal grain size is smaller than that of the conventional one, it is possible to suppress stress migration defects caused by the large crystal grain size.
〈実施例〉
以下、図面を用いて本発明の一実施例を詳述するが、本
発明はこれに限定されるものではない。<Example> Hereinafter, an example of the present invention will be described in detail using the drawings, but the present invention is not limited thereto.
第１図は本発明の一実施例を説明するための断面図であ
る。Ｓｉ基板１上にＰＳＧ等の絶縁膜２を形成し、配線
用のコンタクトホール３を形成する。次いで前記Ｓｉ基
板１上にスパッタ法により２０００〜３０００λの膜厚
のＴｉ−Ｗ層４を形成し、更に蒸着或いはスパッタ法に
より０．７μｍの膜厚のＡｌ・Ｓｉ層５を形成した後、
前記Ｔｉ・Ｗ層４とＡＩ！・Ｓｉ層５とを所望する配線
パターンにパタ一二ソグする。このように配線パターン
を形成した半導体基板１金ランプアニール装置にて４０
０〜６００℃下で数十秒間プリアニールしてＴ ｉｒ
Ｗ系の合金をＡＩ Ｓｉ層５中に混入させる。次にこの
半導体基板１上に層間絶縁膜を従来公知の技術で形成し
、前記層間絶縁膜に選択的にスル−ホールを設けた後層
聞納縁膜上Ｖｃ２層めの配線を形成する。FIG. 1 is a sectional view for explaining one embodiment of the present invention. An insulating film 2 such as PSG is formed on a Si substrate 1, and contact holes 3 for wiring are formed. Next, a Ti-W layer 4 with a thickness of 2000 to 3000 λ was formed on the Si substrate 1 by sputtering, and an Al/Si layer 5 with a thickness of 0.7 μm was further formed by evaporation or sputtering.
The Ti/W layer 4 and AI! - Pattern the Si layer 5 into a desired wiring pattern. The semiconductor substrate with the wiring pattern formed in this way was heated for 40 minutes using a gold lamp annealing device.
Pre-anneal for several tens of seconds at 0 to 600°C.
A W-based alloy is mixed into the AI Si layer 5. Next, an interlayer insulating film is formed on this semiconductor substrate 1 by a conventionally known technique, and a second layer of Vc wiring is formed on the rear-layer inner edge film in which through-holes are selectively provided in the interlayer insulating film.
第２図は本発明の一実施例と従来例を比較した図でおり
、横軸は配線材料の結晶粒径（μｒｒＬ）、縦軸はヒロ
ック数（’７Ｂ）を示す。同図中Ａは本発明の実施例に
よるものであシ、形成した配線をランプアニール装置を
用いて１０秒間４００〜６００℃下でプリアニールして
合金化した後、層間絶縁膜形成時の熱処理に代わるもの
として１時間、４４０℃の電気炉アニールを行なったも
のである。FIG. 2 is a diagram comparing an embodiment of the present invention with a conventional example, in which the horizontal axis shows the crystal grain size (μrrL) of the wiring material, and the vertical axis shows the number of hillocks ('7B). In the figure, A is according to an embodiment of the present invention. After the formed wiring is pre-annealed at 400 to 600°C for 10 seconds using a lamp annealing device to form an alloy, it is subjected to heat treatment when forming an interlayer insulating film. As an alternative, electric furnace annealing was performed at 440° C. for 1 hour.
同図中Ｂは配線としてＡ４・Ｓｉ層の単層膜を用い、プ
リアニーｌｖ′ｆ：行なわず１時間、４００〜６００℃
の電気炉アニールを行なったものである。B in the same figure uses a single layer film of A4/Si layer as wiring, pre-annealing lv'f: 1 hour, 400-600°C
It was annealed in an electric furnace.
同図中Ｃは配線としてＡＩ Ｓｉ層の単層膜を用い、ラ
ンプアニール装置で４００〜６００℃下、１０秒間のデ
リア二一μを行なった後、１時間、４４０℃の電気炉ア
ニールを行なったものである。C in the same figure uses a single layer of AI Si layer as the wiring, and after performing Delia 21 μ for 10 seconds at 400 to 600°C in a lamp annealing device, electric furnace annealing at 440°C for 1 hour. It is something that
同図中りは配線としてＴｉ−Ｗ層上にＡｌ−８ｉ層を形
成したものを用い、プリアニールを行なわず１時間４０
０〜６００℃の電気炉アニールを行なったものである。In the middle of the figure, a wire with an Al-8i layer formed on a Ti-W layer was used, and no pre-annealing was performed for 1 hour.
Electric furnace annealing was performed at 0 to 600°C.
配線の結晶粒径は、同図Ａ。The crystal grain size of the wiring is shown in Figure A.
Ｃの如くプリアニールを行なった場合、そのプリアニー
ル温度に依存し、同図中Ｂ、Ｄの如く電気炉アニールの
みを行なった場合、そのアニール温度に依存する。When pre-annealing is performed as shown in C, it depends on the pre-annealing temperature, and when only electric furnace annealing is performed as shown in B and D in the figure, it depends on the annealing temperature.
同図から明らかなように、同図中Ｂの如く配線としてＡ
ｊ？−５ｉ層の単層膜を用い、電気炉アニー〜のみを行
なったものに対して、同図中Ｃに示される従来例のよう
に配線としてＡＡ’−５ｉ層の単層膜を用い、プリアニ
ールを行なった後電気炉アニー１１／ｆ行なうことによ
り、ヒロック数が減少し、また同図中りに示される他の
従来例のように配線としてＴｉ −Ｗ層上にＡｌ・Ｓｉ
層を形成したものを用い、電気炉アニールのみを行なう
ことにより、結晶粒径が小さくなり、更にヒロック数も
減少していることがわかる。しかし、同図中Ａ。As is clear from the figure, as shown in B in the figure, the wiring A
j? In contrast to the one in which a single-layer film of -5i layer was used and only annealing was performed in an electric furnace, a single-layer film of AA'-5i layer was used as wiring as in the conventional example shown in C in the same figure, and pre-annealing was performed. By performing electric furnace annealing 11/f after performing the above, the number of hillocks is reduced, and as in the other conventional example shown in the same figure, Al/Si is formed on the Ti--W layer as wiring.
It can be seen that by using a layered material and performing only electric furnace annealing, the crystal grain size is reduced and the number of hillocks is also reduced. However, A in the same figure.
に示される本発明の実施例では、同図中Ｃに比べて大幅
に結晶粒径が小さくなり、更には同図中Ｃ１Ｄに比べて
大幅にヒロック数か減少しており、３μｍ以下の結晶粒
径においても十分なヒロック抑制効果が現われていると
いえる。In the example of the present invention shown in FIG. It can be said that a sufficient hillock suppression effect is exhibited also in the diameter.
このように配線としてＴｉ−Ｗ層層上にＡｌ・Ｓｉ層を
形成し、これにプリアニー／ｌ／を行なってＡＪＳｉ層
中にＴ ｉ ＋’ Ｗ系の合金を混入させることにより
、ＡＪの粒界拡散が抑制され、結晶成長が抑制される。In this way, an Al/Si layer is formed on the Ti-W layer as a wiring, and by pre-annealing /l/ to mix the Ti +' W alloy into the AJSi layer, the AJ grains Field diffusion is suppressed and crystal growth is suppressed.
〈発明の効果〉
本発明により、結晶粒径が３μｍ以下であってもヒロッ
ク成長半抑制効果が現れ、同時にストレヌマイグレーシ
コン不良も抑制できるため、短絡、クラック、或いは断
線等による半導体装置不良が発生し雌しくなる。したが
って本発明は、信頼性及び歩留りの高い半導体装置の製
造に寄与するものである。<Effects of the Invention> According to the present invention, even when the crystal grain size is 3 μm or less, a hillock growth semi-suppressing effect appears, and at the same time, it is possible to suppress strain migration silicon failures, so semiconductor device failures due to short circuits, cracks, or disconnections can be prevented. It develops and becomes feminine. Therefore, the present invention contributes to manufacturing semiconductor devices with high reliability and high yield.
第１図は本発明の一実施例を説明するための断面図、第
２図は本発明の一実施例と従来例とを比較するためのグ
レインサイズ−ヒロック数ヲ表ス図である。
代理人 弁理士 杉 山 毅 至（他１名）菓 ｌｙ
！Ｊ
第２図 自少田も≠隠矛（μｍ）FIG. 1 is a sectional view for explaining an embodiment of the present invention, and FIG. 2 is a grain size-hillock number table for comparing the embodiment of the present invention and a conventional example. Agent: Patent Attorney Takeshi Sugiyama (and 1 other person)
! J Figure 2 Self-shoda mo ≠ Hidden spear (μm)
Claims (1)
・Ｗ層とＡｌ・Ｓｉ層とを順次形成し、前記素子間を電
気的に相互接続する配線として前記Ｔｉ・Ｗ層とＡｌ・
Ｓｉ層とをパターニングする工程と、 前記半導体基板をプリアニールしてＡｌ・Ｓｉ層をＴｉ
・Ｗ層と合金化する工程とを有し、Ａｌ・Ｓｉ−Ｔｉ・
Ｗの結晶粒径は３μｍ以下にしてなることを特徴とする
配線の製法。 ２、上記プリアニールはランプアニールを用いることを
特徴とする特許請求の範囲第１項記載の配線の製法。[Claims] 1. Ti is deposited on the main surface of a semiconductor substrate on which a plurality of elements are formed.
・A W layer and an Al/Si layer are sequentially formed, and the Ti/W layer and the Al/Si layer are used as wiring for electrically interconnecting the elements.
A step of patterning the Al/Si layer and a step of pre-annealing the semiconductor substrate to change the Al/Si layer to Ti.
・It has a step of alloying with the W layer, and has a process of alloying with the W layer, and has a process of alloying with the W layer,
A method for manufacturing wiring characterized in that the crystal grain size of W is 3 μm or less. 2. The wiring manufacturing method according to claim 1, wherein the pre-annealing uses lamp annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18934087A JPH01272138A (en) | 1987-07-29 | 1987-07-29 | Manufacture of wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18934087A JPH01272138A (en) | 1987-07-29 | 1987-07-29 | Manufacture of wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01272138A true JPH01272138A (en) | 1989-10-31 |
Family
ID=16239698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18934087A Pending JPH01272138A (en) | 1987-07-29 | 1987-07-29 | Manufacture of wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01272138A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02162727A (en) * | 1988-12-15 | 1990-06-22 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH02307218A (en) * | 1989-05-22 | 1990-12-20 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US5421974A (en) * | 1993-04-01 | 1995-06-06 | Advanced Micro Devices, Inc. | Integrated circuit having silicide-nitride based multi-layer metallization |
-
1987
- 1987-07-29 JP JP18934087A patent/JPH01272138A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02162727A (en) * | 1988-12-15 | 1990-06-22 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH02307218A (en) * | 1989-05-22 | 1990-12-20 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US5421974A (en) * | 1993-04-01 | 1995-06-06 | Advanced Micro Devices, Inc. | Integrated circuit having silicide-nitride based multi-layer metallization |
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