JPS63298174A - Ic test system - Google Patents

Abstract

PURPOSE:To facilitate the preparation of a test program, by controlling a plurality of lower-order processors for executing the test program by lines with a higher order processor which controls the execution of the test program. CONSTITUTION:A plurality of lower-order processors 23A-23N are connected to a higher-order processor 21. The processor 21 decides whether a program line read is executed or not checking progress in a test for an element to be tested and assigns actual execution of the program line decided to be executed to any of the processors 23A-23N connected at a lower order. The processors 23A-23N are a speciality processor suitable for the control of a test signal to be supplied to the element being tested through hardware modules 25A-25N and are able to control the modules 25A-25N with limited instruction words.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an IC test system for testing an element under test having a large number of input/output terminals.

"Prior Art" FIG. 2 is a diagram showing an example of the configuration of a conventional IC test system. In the IC test system, a program describing a test sequence for testing the device under test is stored in a storage device (not shown), and the central processing bag W11 reads the test program from the storage device and executes it sequentially. For example, the central processing unit 11 controls all test operations for testing semiconductor memory devices.

Hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 via control lines 12, and the control signals output by the central processing unit 11 as it decodes and executes the test program are these. Hardware module 13A.

13B, 13C to 13N through the control line 12. Although not shown in the figure, the device under test is equipped with input/output terminals ranging from several to several dozen or more, and the hardware modules 13A, 13B, 13C to 13N supply signals to these input/output terminals, and controlled to measure the signal.

The control signal is, for example, a control signal for supplying a 5.25V DC signal to a predetermined input terminal of the device under test, and when this control signal is supplied, for example, the hardware module 13A A 5.25V DC signal is supplied to the designated input terminal of the device under test.

Further, the control signal outputted by the central processing bag 211 is, for example, a control signal instructing to measure a signal, and for example, the hardware module 13B for measuring DC voltage.
When supplied with this control signal, it is connected to a designated output terminal of the device under test and measures the signal voltage.

These hardware modules 13A, 13B.

The microprocessor 14 may be incorporated in 13C to 13N. Even if a huge number of logic elements are required if the test circuit is constructed using only general-purpose logic elements, the circuit board can be made compact by constructing many parts of the logic circuit using the microprocessor 14. The microprocessor 14 in this case is merely a substitute for a large number of logic elements, and only processes a predetermined sequence, and is not used in a way that requires complex judgment functions.

``Problem to be solved by the invention'' The central processing unit decodes and executes a program, that is, outputs control signals for testing the device under test to a hardware module, etc., and also outputs control signals from the device under test. It is necessary to perform all arithmetic controls necessary for the operation of the IC test system, such as measuring signals and determining whether the measurement results are good or bad.

In particular, current signal human power - voltage signal output characteristics (IV characteristics)
Alternatively, a DC test that tests the voltage signal human power - current signal output characteristics (V-, 1 characteristic), etc., requires high-speed and accurate signal control or Measurement of the signal is required. For example, even if a 5.25V signal written in the test program is supplied to the device under test, the central processing unit
．． It is necessary to convert the voltage value of 25 V into a digital data value and supply it to the hardware module, or to calculate and provide the signal voltage up to the timing when the hardware module actually outputs the signal voltage to the device under test. Furthermore,
If the output characteristics of the hardware module deviate from linearity, it is necessary to output digital data that has been corrected by referring to a correction table that stores digital data specifying voltage values in advance. .

Also, when measuring the output signal from the output terminal of the device under test, data is sent to change the measurement range of the hardware module according to the signal, the range is changed, and the signal is measured. The measured values are corrected using a correction table as necessary. The determined measurement value may be compared with a predetermined judgment table to determine whether it is good or bad, or to rank the degree of good or bad.

Because the central processing unit is required to handle all of this for dozens of input/output terminals,
The time required for arithmetic processing by the central processing unit increases.

Therefore, test control of signal output and signal measurement for the device under test through the hardware module becomes slow, making it difficult to increase the test speed of the IC test system.

"Means for Solving Problems" In the present invention, the content of a test sequence by a test program is written line by line in a high-level language, and a higher-level processing device controls execution of the test program line by line. The actual decoding and execution of the control content described in the program line is entrusted to multiple lower-level processing units controlled by the higher-level processing unit, and each lower-level processing unit decodes the program line and dedicates it to the This command system is used to access hardware modules or update test status.

That is, at least one hardware module is connected to each of these lower-level processing units, and these hardware modules operate under control signals output as the lower-level processing unit decodes and executes program lines. The device is configured to generate a test signal for the device under test or measure a signal output from the device under test.

"Operation of the Invention" According to the configuration of the present invention, a higher-level processing device simply decides to execute a test program line by line, requests multiple lower-level processing devices to execute the test program, and writes the code in the program line. It does not actually decipher or execute the controlled contents.

Instead, the decoding and execution of the program lines is performed in a distributed manner by a plurality of dedicated processing units connected below.

In addition, programs can be written concisely in a high-level language line by line without worrying about detailed conditions specific to the device under test. Debugging when making changes is easy.

Embodiment FIG. 1 is a block diagram showing an embodiment of an IC test system of the present invention. The IC test system of the present invention is configured with a plurality of processing devices arranged in a hierarchical structure. That is, although not shown in the figure, there is a higher-level processing device 21 that controls the execution of a test program stored in a storage device, and a higher-level processing device i21 that is connected to this higher-level processing device i21 via a control bus 22. A plurality of lower-level processing devices 23A, 23B that actually execute program lines under the control of the processing device 21
.

23C to 23N and a lower processing device 23A.

Control lines 24A and 24B are connected to 23B and 23C to 23N.

It is hierarchically composed of hardware modules 25A, 25B, and 25C to 25N that are controlled through 24C to 24N.

That is, according to the present invention, the procedure for testing the device under test is stored in the storage device as a test program. In a test program, test procedures are written line by line. For example, commands to set input conditions for input terminals of the device under test, commands to measure output signals output from output terminals, etc. are concisely described in program line units. The higher-level processing device 21 sequentially reads the test program from the storage device program line by program line, and controls whether or not to execute the read program line.

That is, a plurality of lower processing bags M23A, 23B, 23C to 23N are connected to this upper processing device 21,
The upper processing unit 21 determines whether or not to execute the read program line while checking the progress of the test on the device under test, and the actual execution of the program line that has been decided to be executed is carried out by the lower-level processing unit it. :'3 A, 23
B, 23C to 23N.

Each processing device 23A, 23B, 23C to 23N sends a test signal to the device under test to the hardware module 2j.
A, 25B, 25C to 25N is a dedicated processing device suitable for controlling via the hardware module 2.
It is a dedicated processing device suitable for measuring the signals output by the device under test via the hardware modules 25A, 25B, 25C to 25N.
It has an efficient command system for accessing any of the 5Ns and changing test conditions (terminal connections and measuring instrument conditions), and is converted into macro commands. Therefore,
Hardware modules 25A, 25B with a small number of instruction words, for example 1 or 2 instruction words.

It is also possible to control 25C to 25N.

For example, the lower processing devices 23A and 23B.

23C to 23N are hardware modules 25A, 2
5B, 25C to 25N can be controlled to take in the measured data and store it in the storage device with a single command. The upper processing unit 21 uses the high-level language system used in the hardware modules 25A, 25B, 25C~
A processing speed several tens of times faster than directly performing the same control for 25N can be obtained. Therefore, by varying the test conditions applied to a device under test that has a large number of input/output terminals,
It is possible to proceed with the C test at high speed and by using accurate timing signals, such as examining -1 characteristics and IV characteristics.

When the processing device 23 is entrusted with the execution of a program line by the higher-level processing device 21, it decodes the program line and begins actual execution of the program line. In other words, the processing device 23 stores a control program in its storage device (not shown in the figure) that describes the procedure for inputting and outputting test signals to and from the device under test, and uses the result of decoding a given program line to The control program is read and the procedure for controlling the input/output of the signals described in the program line is executed.

These procedures, for example, first decode a given program line and access the designated hardware module 25. Next, change the test status. As explained in the input/output processing of the conventional example, this is a process for supplying, for example, a 5.25V DC signal to the device under test, and a process for measuring the output signal of the device under test. be.

Furthermore, in the present invention, the processing device 23 not only executes the program line that has been entrusted to execute from the higher-level processing device 21, but also decodes the program line and sends the result of the decoding to the edge test element. Functional conditions for which information is given in advance, such as minimum cross width, input conditions,
Output the test signal to the device under test while checking the timing relationship or prohibition conditions, and making judgments to avoid giving an incorrect input signal or falling into a signal state that could even cause damage to the device under test. Alternatively, it is programmed to control the measurement of the output signal.

For example, when a device under test is in test state Q1 during a test, if a signal is applied to the input terminal as a command written in a program line in order to change to the next test state Q2, the device under test is placed. In some cases, the user may fall into the prohibited state Q3, which is not possible. By executing the program line, the processing device 23 checks whether or not the device under test is in the prohibited state Q3.
A control procedure that avoids step 3 is determined and the program line is executed. For example, the processing device 23 determines the control operation and executes the program line so that the state of the device under test reaches the state Q2 described in the program line from state Q1 through state Q4, state Q5, and so on. Execute.

Therefore, when creating a program, it is not necessary to write the program lines while taking into account the prohibited state Q3 of the device under test, and the processing device 23 makes a judgment based on the information supplied in advance. The control is designed to avoid falling into the prohibited state Q3. Therefore, the device is configured to prevent the device under test from malfunctioning and producing erroneous test results due to the device under test entering a prohibited input/output state and being destroyed or falling into an undefined state.

Furthermore, the processing device 23 can not only measure the applied signal, but also perform linear correction, logarithmic curve correction, or change of the measurement range of the measured signal as necessary. The measurement data obtained by processing in this manner is compared with a reference value, a dark value, etc., and its quality is determined, and the data is logged.

In addition, the hardware module 2 that must be controlled
The number of lower processing devices 23A, 23B, 23C to 23N increases or decreases depending on the number of circuits 5A, 25B, 25C to 25N. Since the upper processing device 21 does not actually execute the test described in the program line, 10 or more lower processing devices 23A, 23B, 23C to 23
N can be controlled simultaneously.

In this invention, lower processing devices 23A and 23B.

The input/output control signals output when 23C to 23N actually execute the program line are sent to the hardware module 25A.
, 25B, 25C to 25N. Hardware modules 25A, 25B.

25C to 25N are test signals 2, for example, a 5.25V DC signal is output to a separately designated input terminal of the device under test according to the supplied control signal, or a signal from a designated output terminal of the device under test. is measured.

These hardware modules 25A, 25B.

25C-25N may include a microprocessor 26 similar to conventional IC test equipment. This microprocessor 26 replaces a large number of logic elements and performs a determined sequence without a so-called judgment function at high speed. This microprocessor 26 is a general-purpose processor, and is preprogrammed with Go/No-Go operations, and can control the input/output of signals to and from the device under test by instructions from the processing unit 23.

As described above, in the present invention, a command word system suitable for controlling the hardware module 25 is provided under the upper processing device 21 using a general-purpose programming language, and a lower processing word system dedicated to controlling the hardware module is provided. ! 23A,
A distributed processing system with a hierarchical structure in which 23B, 23C to 23N are arranged was constructed. In other words, the lower processing word W23
A, 23B.

23C to 23N perform actual processing of testing the device under test (the input/output terminals of the device under test and the hardware module 25A) under the control of the upper processing device 21.

Connection with 25B, 25C to 25N, data setting.

Functional decentralization was achieved by performing all functions (signal measurement, correction, pass/fail judgment, recording of measurement results, etc.).

"Effects of the Invention" As explained above, in the past, when testing semiconductor devices, test sequences that could not be divided and executed were processed by one processing device, but according to the present invention, ,
A plurality of processing devices are arranged in a hierarchical manner, and the upper processing device exclusively controls the execution of program lines, and the actual execution of the program lines is performed by the lower processing devices. In other words, the upper-level processing unit determines when to execute a program line written in a high-level language and allocates execution to each lower-level processing unit, controlling the organic operation of the entire IC test system. A dedicated processing unit was installed, and control was adopted in a hierarchical structure in which the actual execution of program lines was distributed to a plurality of lower-level dedicated processing units. In this way, along with the improvement in processing speed due to distributed architecture, high-level languages that are easy to program are used for upper-level processing units, and language systems suitable for understanding and controlling the high-level languages are being developed. use.

Furthermore, the lower-level processing device is instructed by the higher-level processing device to convert it into macro instructions using a command word system suitable for high-speed control of the hardware module. Therefore, the processing from decoding a program line to outputting a control signal by the processing device becomes extremely fast, and a test on the device under test, especially a DC test, can be performed at high speed.

Furthermore, since the test program for the device under test can be written line by line in a high-level language, the test program can be easily modified and debugged.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an IC test system according to the present invention, and FIG. 2 is a block diagram showing an example of the structure of a conventional IC test system. 11: central processing unit, 12: control line, 13 hardware module, 14: microprocessor, 21: upper processing unit, 22: control bus, 23: lower processing unit,
24: Control line, 25 Hardware module, 26:
microprocessor.

Claims (1)

[Claims] (1) A higher-level processing device that controls the execution of the test program, and multiple lower-level processes that are controlled by the higher-level processing device and execute instructions that access the test program line by line module and instructions that update the test status. IC test consisting of a device and multiple hardware modules that are controlled by one of the lower processing units and generate test signals for the device under test and measure the output signals of the device under test in accordance with the execution of instructions. system.