JPS63298173A - Integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of pins provided for testing, by inputting a test mode set value from a pin used as output pin to set an internal circuit to a test mode. CONSTITUTION:An operation mode control circuit 1 has input terminals 100-103 and output terminals 104-110. An input pin 2 receives an input of a reset signal for initializing the whole of an internal circuit of an LSI. Terminals 4, 6 and 8 act as output pin when a reset signal is at H and does as input pin to receive inputs of signals TEST 1, 2 and 3 for setting a test mode when it is at L. When the reset signal is at H, output signals 201-203 from the internal circuit are outputted at the pins 4, 6 and 8 and those TEST 1, 2 and 3 are inputted into the terminals 101-103 at the pins 4, 6 and 8 when it is at L.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a test method for testing the operation of the internal circuit of an integrated circuit (hereinafter referred to as LSI), in which the internal circuit is divided into a plurality of blocks and By combining the values of test signals input from pins normally used as output pins when the reset signal is active, it is possible to set a test state in which only one block is active, reducing the number of pins specifically provided for testing. This provides an LSI with improved performance.

2. Description of the Related Art A block diagram of a test state setting section of a conventional LSI is shown in FIG. In FIG. 3, 2 is an input pin for initializing the entire internal circuit of the LSI, and 3 is an input pin for inputting the reset signal.

Reference numeral 14 is an input pin for inputting the signal TEST1 for setting the test mode, and reference numeral 15 is an input cover sofa for the TIC8T1 signal. 16 is a signal TEST2 for setting the test mode
An input pin 17 is an input buffer for the TEST2 signal. 18 is a signal T for setting the test mode
Input pin 19 for inputting EST3 is an input cover sofa for the TEST3 signal. Reference numeral 10 denotes a decoder circuit such as an LSI 38 in TTL, which includes input terminals 1001, 1002, 1003, and an output terminal 1004.

1005, 1006, 1007, 1008, 100
It has 9°1010.1011. TESTl, TEST2. for setting the test mode. Each signal of TEST3 is input to the input terminals 1001 and 1002 of the decoder circuit 10, respectively.
It is connected to ゜1003.

The operation of the conventional LSI test state setting section configured as described above will be described below.

Values input from input pins 2, 14, 16.18 and output pins 104, 106, 106, 107°108, 1
Table 1 shows the results of the values output from 09 and 110.

According to Table 1, if the reset signal input from input pin 2 is "L", all internal circuit blocks are in their initial state. When the reset signal is "H", only one of the internal circuit blocks becomes operational depending on the values of the test mode setting signals TEST1°TR8T2 and 'rxs'r3. Furthermore, when the inputs from TEST1, TEST2, and TEST3 are all at H'', all internal circuit blocks are in the operating state.

As described above, in the conventional LSI, the operating state of its internal circuit is determined by the value of the test mode setting pin.

(Margins below) 5 Hage Table 1 61\-7゛Problems to be solved by the invention In such conventional LSIs, as the circuit scale increases, the number of test pins increases, and the number of trench pins is limited. In LSIs, sufficient test pins were not available, and effective testing was not performed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an LSI in which the number of pins provided for internal circuit testing is significantly reduced.

Means for Solving the Problems The present invention provides a reset signal input pin that initializes the entire internal circuit, and a pin that operates as an output pin when the reset signal is inactive, and a pin that operates as an output pin when the reset signal is inactive. When the reset signal is active, the test signal input from the input/output pin is equipped with multiple input/output pins that operate as input pins and an operation mode control circuit that sets the operation mode of the internal circuit. 71\- is the same as the test mode in which a part of the internal circuit specified by the test signal is decoded and operated, and when the input test signal is the reset mode setting value, all the internal circuits are initialized. When the reset mode is set and the reset signal is inactive,
This integrated circuit is characterized by being in an operation mode in which all internal circuits are operated.

Effect of the Invention With the above-described configuration, the present invention allows the internal circuit to be set to the test mode by inputting the test mode setting value from the pin normally used as an output pin when the reset signal essential to the LSI is in the active state. In particular, the number of pins provided can be significantly reduced.

Embodiment FIG. 1 is a block diagram of an embodiment of a test state setting section in an integrated circuit according to the present invention. In FIG. 1, 1 is an operation mode control circuit, and input terminals 100, 101, 1
02,103. Output terminals 104, 105, 106, 10
It has 7,108,109°110. Reference numeral 2 is an input pin for initializing the entire internal circuit of the LSI or inputting a clock signal, and reference numeral 3 is an input buffer for the reset signal.

4.6.8 works as an output pin when the reset signal is "H", and serves as an input pin for inputting the test mode setting signal TEST1.2.3 when the reset signal is "L"'. 5.7.9 are input/output buffers connected to the input/output pins, respectively. That is, when the reset signal is "H", the output signal 2o1゜202.203 from the internal circuit is output to the input/output pins 4 and 6.
．． 8, and when the reset signal is L', the test signals TEST1, TEST2 . T.E.
ST3 is input from input/output pins 4, 6.8 to input terminals 101, 102, 103 of the operation mode control circuit.

FIG. 2 is a circuit diagram showing an embodiment of the operation mode control circuit of FIG. 1, in which 10 is a decoder circuit, and has input terminals 1001, 1002, and 1003.

Output terminal 1o○4, 1005, 1006, 100
? .

It has 1008.1009, 1010.1011. TESTl and TEST2 for setting the test mode.

Each of the nine signals TEST3 is input to input terminals 1001, 1002, and 1003 of 10 decoder circuits, respectively.

The operation of the test state setting unit in the integrated circuit of the present invention configured as described above will be described below.

Values input from input pin 2 and input/output pins 4, 6.8 and output terminals 104, 105, 106, 107° 108,
Table 2 shows the results of the values output from 109 and 110. According to Table 2, when the reset 7) signal input from input pin 2 is "L", test mode setting signals TEST 1 , TEST 2 .
Depending on the value of TEST3, only one of the internal circuit blocks becomes operational.

When the input/output pins 4, 6, and 8 are still in a high impedance state, the input terminals 101, 102, and 10 are input to the operation mode control circuit by the internal pull-up resistors.
All values of 3 become "Hu" state, and all internal circuit blocks become initial state. When the reset signal is still "H", input/output pins 4, 6.8 work as output pins, and all internal circuits operate. become a state.

1o'・-7゛Table 2 11 In the normal operating mode of this LSI, the input/output pins 4.6.
8 is connected to the input pin of another LSI, so when the reset signal is L°, the input/output buffers 5, 7, and 9 are in a high impedance state, but due to the internal pull-up resistor, the input pin of the decoder circuit are all set to "H", and the entire internal circuit becomes the initial state as shown in Table 2.In addition, in the test mode, the reset signal is set to "L" and the test mode is set from input/output pins 4, 6.8. All you have to do is input the signal and test the internal circuit blocks one by one.

Effects of the Invention As described above, according to the present invention, the number of pins provided especially for I and SI tests can be significantly reduced with an extremely simple configuration, and its practical effects are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the test state setting section in the integrated circuit of the present invention, FIG. 2 is a block diagram showing an embodiment of the operation mode control circuit in FIG. 1, and FIG. 3 is a conventional block diagram. FIG. 2 is a block diagram showing an example of a test state setting section in the integrated circuit of FIG. 1... Operation mode control circuit, 2... Reset signal input pin, 4, 6.8... Input/output pin, 10... Decoder circuit.

Claims (2)

[Claims] (1) A reset signal input pin that initializes the entire internal circuit; when the reset signal is inactive, it operates as an output pin; when the reset signal is active, it operates as an input pin. It is equipped with a plurality of operating input/output pins and an operation mode control circuit that sets the operation mode of the internal circuit, and the operation mode control circuit controls the test signal input from the input/output pin when the reset signal is active. The test mode is set to decode and operate a part of the internal circuit specified by the test signal, and when the input test signal is the reset mode setting value, the reset mode is set to initialize all the internal circuits. An integrated circuit characterized in that when a reset signal is inactive, the integrated circuit is in an operation mode in which all internal circuits are operated. (2) The integrated circuit according to claim 1, wherein when the test signal input pin is in a high impedance state, the integrated circuit enters a reset mode in which all internal circuits are initialized by an internal pull-up resistor.