JPS6235273A - Test system for output buffer - Google Patents

Abstract

PURPOSE:To test an output buffer easily and rapidly, by providing a 3-input selector circuit having input for logical values '0', '1' between an internal circuit of an integrated circuit and an output buffer. CONSTITUTION:Between internal buffer (internal circuit) 1 of an integrated circuit 1 and each output buffer 3 are provided 3-input selector circuits 10, 20, which are supplied respectively with data output, logical value S1 from the circuit 1 and logical values '0', '1' and control output and logical output S2 from the circuit 1 and logical values '0', '1'. Normally, signals S1, S2 are selected, and if the output S2 is '1' the buffer 3 outputs S1, while if the output S2 is '0' the output impedance of the buffer 3 makes high impedance independently of the signal S1. On the other hand, the circuits 10, 20, when controlled by decoder output, select required logic values respectively, and output them for the setting of test data and test control data. Thus, an easy and rapid test of an output buffer is available without changing the input pattern of the circuit 1.

Description

[Detailed Description of the Invention] [Summary] In an integrated circuit having an output buffer, a selection circuit with three inputs is provided before the input terminal and the control terminal of the output buffer, and the logic of the signals input to the input terminal and the control terminal is By allowing the value to be set arbitrarily, it is possible to test the output buffer easily and in a short time.

[Industrial application field]

TECHNICAL FIELD The present invention relates to an improvement in an output buffer sofa testing method for integrated circuits with output buffers.

FIG. 4 is a diagram showing an example of an integrated circuit to which the present invention is applied.

In FIG. 4, an internal circuit 1 transmits a signal S to an input terminal 4 and a control terminal 5 of a plurality of output buffers 3 based on a binary signal pattern input from a plurality of input terminals 2.
Set the logical values of 1 and S2.

Each output buffer 3 receives a signal s2 input to a control terminal 5.
When is the logic "1", the signal s3 having the same logic value as the signal s1 is output from the output terminal 6, and when the signal s2 is the logic "0", the output impedance of the output buffer 3 is the same as that of the input terminal 4. The impedance becomes high regardless of the logical value of the signal s1 input to the circuit.

In this kind of integrated circuit, the test of each output sofa is
It is desired that it be implemented as easily and quickly as possible.

[Conventional technology]

In a conventional output buffer test method, the binary signal pattern input to each input terminal 2 of the integrated circuit is varied, and the logical values of the signals S1 and s2 transmitted from the internal circuit 1 to each output buffer 3 are varied. Due to this, we were conducting a test of Dekaba Sofa 3.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional output cover sofa testing method, in order to test the output cover sofa, it is necessary to input various binary signal patterns from the input terminal, the test method is complicated, and the required time is There was also a risk that it would increase.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, a three-input selection circuit 10.20 is provided in front of the input terminal and control terminal of the output buffer 3, and the first input terminal of each selection circuit 10.2o is connected to the input terminal from the internal circuit 1. The signals 31 and S2 are inputted, the logic "0" signal and the logic "1" signal are respectively inputted to the second and third input terminals, and each selection circuit 10.20 is connected to the second
The output buffer 3 is tested by setting one of the input terminals and the third input terminal to be selected.

[Effect]

That is, according to the present invention, it is possible to input signals of arbitrary logical values to the input terminals and control terminals of the output buffer sofa depending on the setting method of each selection circuit, so that it is possible to easily and quickly test the output buffer.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an output buffer test method according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating the transfer gate in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, each selection circuit 10 and 20 includes three transfer gates 11 to 13 and two transfer gates, respectively.
Consists of 1 to 23. Transfer gates 11 and 21 receive signals sl and S2 output from internal circuit 1, respectively, and transfer gate -12
A logic "O" signal is always input to the transfer gates 13 and 22, and a logic "1" signal is always input to the transfer gates 13 and 23.

Each transfer gate 11 to 13 and 21 to 23
As shown in FIG. 3, it is composed of two MOS transistors and two inverters, and becomes conductive when the input control signal 5i (i is a to d) is set to logic "0". Therefore, when the control signal si is set to logic "1", a cutoff state occurs.

On the other hand, binary test signals s4 and s5 are input to test terminals 31 and 32, respectively.

When the test signals s4 and s5 input from the test terminals 31 and 32 are both logic "0", the decoder 33
sets the control signal sa transmitted to transfer gates 11 and 21 to logic "1", and sets the control signals sb to sd transmitted to transfer gate 23 via other transfer gates 12, 13, 22 and gate 34 to logic "1".
0". As a result, only the transfer gates 11 and 21 become conductive, and the signals sl and S2 output from the internal circuit 1 pass through the transfer gates 11 and 21 to the input terminal 4 of the output sofa 3 and the control The signal is transmitted to terminal 5. That is, the integrated circuit enters the normal operating state.

Next, the test signal S4 input from the test terminal 31 is
When the test signal S5 input from the test terminal 32 is set to logic "1", the decoder 33
sets the control signal sb transmitted to the transfer gate 23 via the transfer gate 12 and the gate 34 to logic "1", and sets the other control signals sa, sc and sd to logic "O". As a result, transfer gate 1
Only 2 and 23 become conductive, a logic "0" signal is input to the input terminal 4 of the output buffer 3 via the transfer gate 12, and a logic "0" signal is input to the control terminal 5 of the output buffer 3 via the transfer gate 23. A logic "1" signal is input, and a logic "0" output signal S3 is output from the output terminal 6.
is output.

Next, the test signal S4 input from the test terminal 31 is
1” and the test signal S5 input from the test terminal 32 is set to logic “0”, the decoder 33
sets the control signal sc transmitted to the transfer gate 23 via the transfer gate 13 and the gate 34 to logic "1", and sets the other control signals sa, sb and sd to logic "0". As a result, transfer gate 1
Only 3 and 23 are in a conductive state, and the out-cover sofa 30
A logic "L" signal is input to the input terminal 4 via the transfer gate 13, a logic "1" signal is input to the control terminal 5 of the output buffer 3 via the transfer gate 23, and a logic "1" signal is input from the output terminal 6. is the logic “L” output signal S3
is output.

Furthermore, the test signal S input from the test terminals 31 and 32
If both S4 and S5 are set to logic "1",
The decoder 33 sets the control signal sd transmitted to the transfer gate 22 to logic "1" and sets the other control signals sa to sc to logic "0". As a result, only the transfer gate 22 becomes conductive, and the control terminal 5 of the output buffer 3 receives the logic "
The 0° signal is input, and the output impedance of the output buffer 3 becomes a high impedance state.

As is clear from the above description, according to this embodiment, the test signals s4 and s input from the test terminals 31 and 32
By appropriately setting the logical value of 5, the output buffer 3
The logical values of the signals input to the input terminal 4 and control terminal 5 of the output buffer 3 can be arbitrarily set, and the output buffer 3 can be tested easily and quickly.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the three-input selection circuit may include a transfer gate, and the configuration is not limited to that shown in the figures.
Although many other modifications may be considered, the effects of the present invention remain the same in any case.

〔Effect of the invention〕

As described above, according to the present invention, it becomes possible to easily and quickly test an output cover sofa used for an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an output cover sofa test method according to an embodiment of the present invention, FIG. 3 is a diagram illustrating the transfer gate in FIG. 2, and FIG. 1 is a diagram showing an example of an integrated circuit to which the present invention is applied. In the figure, f, 1 is the internal circuit, 2 is the input terminal, 3 is the output sofa, 4 is the input terminal of the output sofa, 5 is the control terminal,
6 is an output terminal, 10 and 20 are selection circuits, 11 to 1
3 and 21 to 23 are transfer gates, 31 and 32 are test terminals, 33 is a decoder, 34 is a gate, and s
1 to S3 are signals, S4 and S5 are test signals, and sa to sd and si are control signals. Thursday, EI Moon's first cover ceremony, Ma Kenzajiryo 1st Ri)

Claims (1)

[Scope of Claims] An integrated circuit comprising an output buffer (3) on the output side of the internal circuit (1), comprising a three-input selection circuit (10 , 20), the signals (s1, s2) from the internal circuit (1) are input to the first input terminals of each of the selection circuits (10, 20), ), a logic "0" signal and a logic "1" signal are respectively inputted to the second and third input terminals, and each selection circuit (10, 20) is connected to one of the second and third input terminals. An output buffer test method characterized in that the output buffer (3) is tested by setting the output buffer (3) to be selected.