JPS6329572A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the stepping resulted from a wiring or a gate electrode by a method wherein the title device is formed into the structure in which the wiring or the gate electrode of an MISFET is buried in the groove provided on a semiconductor substrate. CONSTITUTION:On a static RAM, the field insulating film 2 such as an SiO2 film having a plane shape is selectively provided on the surface of the semiconductor substrate 1 such as a p-type Si substrate and the like, and the isolation of element is performed using said insulating film 2. Also, a groove 1a having a rectangular crosssection, for example, is provided in the substrate 1 of the active region surrounded by the field insulating film 2, and the gate insulating film 3 such as an SiO2 film and the like is provided on the side face of said groove 1a. Then, an n<+> type silicon epitaxial layer, for example, is buried in the groove 1a on which the insulating film 3 is provided, and a word line WL is constituted with the silicon epitaxial layer. As the word line WL is buried in the substrate 1 as above-mentioned, the stepping on the part of an MISFET Q5 can be reduced in the amount of thickness of the word line WL, and the stepping of the memory cell part can also be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a MISF
Static RAM (Random
Access Me+++ory) and Dynamic R
The present invention relates to technology that is effective when applied to AM.

[Conventional technology]

As a static RAM memory cell, so-called complete C
MO8 type Memotsu memory cell (for example, Nikkei Electronics, December 30, 1985 issue, p. 122)
). As shown in FIG. 8, this complete CMO 8 type memory cell channel MISFET Q1 and P channel M
an inverter consisting of I S F E T Q 2, and n
Channel MISFETQ3 and P channel MIS
FETQ, and a flip-flop for storing information configured by connecting the output of one of the two inverters to the input of the other, and a switch for exchanging information between the flip-flop and the outside of the cell. For MIS
It has a configuration in which FET Q5 and Q6 are combined. The p-channel ~II 5FETQ2,
One end of each of Q4 is at power supply potential■. The sources of MISFETs Ql and Q3 are grounded. Furthermore, the M I S F E for the switch
A word line WL is connected to the gates of T Q 5 and Q6, and data lines DL and DL are connected to the drains, respectively.

The present inventor studied a static RAM having a complete CMOS type memory cell as described above. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.

In other words, the word line WL of a static RAM using a complete CMO3 type memory cell is 1. For example, the word line WL of a static RAM using a high-resistance polycrystalline silicon load type memory cell is the first layer wiring, whereas the word line WL is the upper layer aluminum wiring. , silicide wiring, polycrystalline silicon wiring, etc. are used, so the wiring layers are more multilayered.

[Problem that the invention seeks to solve]

However, such a multilayer wiring structure has a problem in that the step difference becomes large in the memory cell portion, which causes an inconvenience.

An object of the present invention is to provide a technique that can reduce steps caused by wiring or gate electrodes.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

That is, the MISFET wiring or gate ff electrode is embedded in a groove provided in a semiconductor substrate.

[For production]

According to the above-mentioned means, since the wiring or the gate electrode is embedded, the step difference can be reduced by the thickness thereof.

〔Example〕

Hereinafter, the configuration of the present invention will be described based on one embodiment with reference to the drawings.

In addition, in all the figures, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. Also,
The memory cell of the static RAM according to this embodiment is the eighth
It has a similar circuit configuration as shown in the figure.

FIG. 1 shows a complete CMO3 type memo type MORISETCH MIS in a static RAM according to an embodiment of the present invention.
FIG. 2 is a plan view showing the configuration near FET, and FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1. FIG.

As shown in FIGS. 1 and 2, in the static RAM according to this embodiment, a semiconductor substrate 1, such as a P-type Si substrate, has a predetermined planar shape on its surface.
A field insulating film 2 such as an O2 film is selectively provided, and element isolation is performed by this field insulating film 2.

In the semiconductor substrate 1 in the active region surrounded by the field insulating film 2, a groove 1a having, for example, a rectangular cross section is provided. For example, on the side surface of this groove 1a, SiO2
A gate insulating film 3 such as a film is provided. and,
For example, an n-type silicon epitaxial layer is buried in the trench la in which the gate insulating film 3 is provided, thereby forming a word line WL. Since the word line WL is embedded in the semiconductor substrate 1 in this way,
M I S F E T by the thickness of this word line WL
The step difference in the Qs portion can be reduced, and therefore the step difference in the memory cell portion can be reduced.

As shown in FIG. 1, the word line WL has a protrusion a that reaches the field insulating film 2, and gate insulating films 3 provided on both sides of the protrusion a completely isolate elements. be exposed.

Furthermore, on the word line WL and the surface of the semiconductor substrate 1,
An insulating film 4 such as a SiO2 film, for example, is provided continuous to the gate insulating film 3. In addition, in Figure 1, M
In order to make the structure of ISFETQ 5 easier to understand, illustration of this insulating film 4 is omitted. On this insulating film 4, there is a wiring 5 made of, for example, a polycrystalline silicon film.
6 are provided parallel to each other. Note that this wiring 5 connects the drains of MISFETQ3 and O4 and MI5FE.
TQ+ is connected to the gate of O2, and the wiring 6 is
Connected to data line DL.

Openings 4a and 4b are provided in the insulating film 4, and in the semiconductor substrate 1 below these openings 4a and 4b, for example, an n-type source region 7 and drain region 8 are provided. Note that the gate electrode, source region 7, and drain region 8 made up of the word aWL constitute a switching M T S FET Q5. The wiring 5.6 is connected to the source region 7 and drain region 8 through the openings 4a and 4b, respectively.

Next, a method for manufacturing the static RAM according to this embodiment configured as described above will be explained.

As shown in FIG. 3, a field insulating film 2 is first formed on the surface of the semiconductor substrate 1 by, for example, selective oxidation, and then a field insulating film 2 is formed on the surface of the semiconductor substrate 1 by, for example, CVD.
After forming an insulating film 9 like a film, a predetermined portion of the insulating film 9 is removed by etching to form an opening 9a. Thereafter, using the insulating film 9 as a mask, the semiconductor substrate 1 is etched by, for example, reactive ion etching (RIE) in a direction perpendicular to the substrate surface, thereby forming a trench 1a having substantially the same shape as the opening 9a.

Next, for example, by thermally oxidizing the semiconductor substrate 1 in the groove 1a, as shown in FIG. :A gate insulating film 3, such as a SiO2 film, is formed on the bottom and side surfaces of the Ha.

Next, the gate insulating film 3 formed at the bottom of the groove 1a is selectively etched away by, for example, RIE, and the fifth
As shown in the figure, after partially exposing the surface of the semiconductor substrate 1, for example, an n° type silicon epitaxial layer is formed on the semiconductor substrate 1 exposed in the groove 1a by, for example, selective epitaxial growth. A word line WL made of an epitaxial layer is formed embedded in the trench 1a. Note that the surface of the word line WL is formed so as to be substantially flush with the surface of the semiconductor substrate 1.

Next, after removing the insulating film 9 by etching, as shown in FIG. Etching is removed to form openings 4a and 4b.

Next, as shown in FIG. 7, after forming, for example, a polycrystalline silicon film 10 on the entire surface by, for example, CVD, this polycrystalline silicon film 10 is doped with an n-type impurity such as arsenic by, for example, ion implantation to reduce the Become a resistance. next,
By performing heat treatment to diffuse the n-type impurity in this polycrystalline silicon film 10 into the semiconductor substrate 1,
As shown in FIGS. 1 and 2, after forming, for example, an n-type source region 7 and drain region 8, the polycrystalline silicon film 10 is patterned into a predetermined shape by etching. Wires S, 6 are formed as shown.

Note that the source region 7 and drain region 8 may be formed by performing heat treatment before patterning the polycrystalline silicon film 10 to diffuse impurities in the polycrystalline silicon film 10 into the semiconductor substrate 1. The source region 7 and drain region 8 are formed by selectively ion-implanting n-type impurities into the semiconductor substrate 1 using a predetermined mask before forming the opening 4a in the process shown in FIG. 6, for example. It is also possible to form

Note that the same process as shown in FIGS. 3 to 5 is
It is described in 1985, IEEE, IEDM, 1985, p. 419. The objective is different from that of this embodiment.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention. It is.

For example, it is also possible to have a structure in which the gate electrode of the MISFET is buried in a groove provided in a temporary semiconductor substrate.
The present invention can also be applied to dynamic RAM.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions will be briefly explained.

It is as follows.

In other words, game) -? l! The step difference can be reduced by the thickness of the pole or word line.

[Brief explanation of the drawing]

FIG. 1 shows an M I for a complete CMO3 type memory cell in a static RAM according to an embodiment of the present invention.
A plan view showing the configuration near the S FET, FIG.
8 are cross-sectional views taken along line A-Ai in the figure, and FIGS. The figure is a complete CMO3 type memory cell circuit diagram of static RAM. In the figure, 1... semiconductor substrate, 2... field insulating film, 3... gate insulating film, 4... insulating film, 5, 6...
・Wiring, 7 ・Source region, 8...Drain region, Q
, ~Q6 No. 1 Fig. 1 (.l wL('A') Hitotoko No. 2 Fig. 7', 7L+) J, 7 of 7(') Fig. 3 Fig. 4 Outside the drawing, 2) Fig. 5''/ (P) Fig. 6 Fig. 7/(lI'''n Fig. 8)

Claims (1)

[Claims] 1. A semiconductor integrated circuit device comprising a MISFET, characterized in that the wiring or the gate electrode of the MISFET is embedded in a groove provided in a semiconductor substrate. . 2. The semiconductor integrated circuit device according to claim 1, wherein the wiring or the gate electrode is made of an n^+ type silicon epitaxial layer. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the wiring is a word line. 4. The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the semiconductor integrated circuit device is a static RAM or a dynamic RAM.