JPS62210666A - Static ram - Google Patents

Abstract

PURPOSE:To decrease current consumption and to implement high speed operation, by constituting high resistance polycrystalline Si resistors so that they are thinner than the interconnection layer, and making it possible to increase the resistance value of the high resistance polycrystalline Si resistors, with the resistance value of the interconnection layer being kept at a low level. CONSTITUTION:The thickness of an N<+> type polycrystalline Si film, which constitutes an interconnection layer 13, is selected to be, e.g., 1,000Angstrom or more. The sheet resistance of the interconnection layer 13 can be reduced to about 100OMEGA/square or less. Therefore, signal delay due to interconnection resistance can be prevented. The thickness of intrinsic polycrystalline Si films, which constitute high resistance polycrystalline Si resistors R1 and R2, is selected to be a value lower than the thickness of the N<+> type polycrystalline Si film constituting the interconnection layer 13, e.g., 500Angstrom or less. Thus the values of the resistance of the high resistance polycrystalline Si resistors R1 and R2 can be made high with the resistance value of the interconnection layer 13 being kept at a low level. Therefore, current consumption can be decreased to about 0.5muA or less.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to static RAM (Random A
In particular, the present invention relates to a technique that is effective when applied to wiring layers in high-resistance polycrystalline Si (silicon) load type memory cells and high-resistance polycrystalline Si resistors.

[Conventional technology]

In recent years, high-resistance polycrystalline Si loaded memory cells have been mainly used as memory cells for static RAM (for example, Japanese Patent Laid-Open No. 57-130461, etc.), No. 4
As shown in the figure, this high-resistance polycrystalline Si load type memory cell consists of an inverter consisting of a MOSFETQ I and a high-resistance polycrystalline Si resistor R1, and a MO3FETQ
It has a flip-flop for information storage configured with an inverter consisting of a high-resistance polycrystalline Si resistor R2 and a high-resistance polycrystalline Si resistor R2, and the output of one of the two inverters is connected to the input of the other. MO3F ETQ3 for switch for exchanging information. It has a configuration in which Q4 is combined. The above-mentioned high resistance polycrystalline Si resistor R1,
One end of each of R2 is connected to the power supply ■co, and also connected to M
The sources of O3FETQ+ and Q2 are grounded. Furthermore, MO5FETQ for the above switch
3. A word line WL is connected to the gate of Q4, and data lines DL and "DL are connected to the train.

The present inventor has discovered that the so-called standby consumption W1. Style■8. .

(current flowing from the power supply VCa to the ground wire through RI or R2 during standby) was studied.

The following is a technique that has been considered by the present inventor, although it is not a publicly known technique, and its outline is as follows.

The above-mentioned high-resistance polycrystalline Si resistors R1 and R2 were formed, for example, as follows. That is, after forming MO8FETQ, ~Q4 with the first layer polycide film as a gate on a semiconductor substrate, and then forming an interlayer insulating film, non-doped, that is, intrinsic
Insic) polycrystalline Si film is formed. Next, of this intrinsic polycrystalline Si film.

The surface of the region including the portion that will later become a high-resistance polycrystalline Si resistor is covered with a mask layer, and this mask layer is used to diffuse phosphorus (P) into the polycrystalline Si film, implant ions, etc. to lower the resistance. . Next, after removing the mask layer, the polycrystalline Si film is patterned into a predetermined shape to form a wiring layer consisting of an n-type polycrystalline Si film whose resistance has been lowered by introducing phosphorus, and an intrinsic polycrystalline Si film. A high resistance polycrystalline Si resistor R+ consisting of a film.

Form R2. As you can see from these explanations.

The thickness of the low resistance n+ type polycrystalline Si film constituting the wiring layer,
The film thicknesses of the intrinsic polycrystalline Si films forming the high-resistance polycrystalline Si resistors Rr and R2 are the same.

Figure 5 shows lff18 and r in static RAM.
Wiring layer made of l” type polycrystalline Si film (phosphorus diffusion condition: 8
75° C. for 30 minutes) is a graph showing the relationship between sheet resistance and polycrystalline s1 film thickness. As shown in Fig. 5, IG
B decreases exponentially as the polycrystalline Si film thickness decreases. In other words, the resistance values of the high-resistance polycrystalline Si resistors R1 and R2 increase exponentially as the polycrystalline s1 film thickness decreases. Note that this tendency is considered to be due in part to the fact that the crystal grain size decreases as the polycrystalline Si film becomes thinner.

[Problem that the invention seeks to solve]

From FIG. 5, it can be seen that in order to reduce Isg, it is sufficient to make the polycrystalline Si film thinner. However, as shown in Figure 5, by thinning the polycrystalline Si film, high resistance polycrystalline
If an attempt is made to increase the resistance values of the i-resistances Rr and R2, the resistance of the wiring layer will also increase accordingly. Therefore, in order to prevent signal delays due to wiring resistance and achieve high-speed operation, polycrystalline silicon is currently only available up to a film thickness of 1.1000mm (approximately 1°007mm in sheet resistance of the wiring layer). It is not possible to make the film thinner. As a result, although there is a demand to reduce I5B to, for example, about 0°1 to lμ8, the current technology is only able to reduce I5B to about 0°1 to lμ8. It is difficult to reduce the current to about 1 μA or less. It is clear that this problem will become even more serious because the polycrystalline Si film will need to be made even thinner in future highly integrated static RAMs that require submicron processes.

An object of the present invention is to provide a technique that can reduce the Isg of a static RAM and increase the speed of operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

That is, the high-resistance polycrystalline Si resistor is made thinner than the wiring layer.

[For production]

According to the above-described means, it is possible to increase the resistance value of the high resistance polycrystalline Si resistor while keeping the resistance value of the wiring layer low. It is possible to achieve a reduction in speed and high-speed operation.

〔Example〕

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. Further, the memory cell of the static RAM according to this embodiment has a circuit configuration similar to that shown in FIG.

As shown in FIGS. 1A and 1B, in the static RAM according to this embodiment, a field insulating film 2 such as a 5102 film is provided on the surface of a semiconductor substrate l such as a p-type Si substrate. Element isolation is performed by field insulation v2. An R9 type channel 1-flange region 3 is provided below this field insulating film 2 to prevent the generation of parasitic channels.

A gate insulating film 4 such as a 5i02 film, for example, is provided on the surface of each active region surrounded by the field insulating film 2. On this gate insulation film 8114 and field insulating film 2, there is a word line WL of a predetermined shape made of a double layer film of, for example, a polycrystalline Si film 5 and a high melting point metal silicide film 6, that is, a polycide film, and a gate I-electrode 7. .8 and a ground line (source line) SL are provided, respectively. Further, in each of the active regions surrounded by the field insulating film 2, an n-type source region 9 and a drain region 10 are formed in self-alignment with the word line WL, gate electrode 7.8, and ground line SL. It is formed. The word line WL, the source region 9 and the drain region 10 form a switch MOS.
F E T Q 3. Q4 is MO5FET with gate electrode 7° source region 9 and drain region lO
MO8FETQ2 is formed by Q1, gate voltage tI8, source region 9, and drain region 10, respectively. Note that the drain region 10 of the MOSFET Q1 and the source region 9 of the MO8FETQ4 are common. Also, these MOS F E
T Q I-Q 4 are all so-called LDD (Lj
ght, ly Doped Drain) structure, and the source region 9 and drain region 10 are formed using semiconductors in two stages, before and after forming sidewalls 11 made of, for example, SiO2 on the side surfaces of the word line WL and gate electrode 7.8. It is formed by introducing an impurity into the group vJ,1.

Furthermore, an interlayer insulating film 12 such as a SiO2 film is provided on each of these MO8FETs Q and Q4. Furthermore, on this glabellar insulating film 12, there is a wiring layer 13 made of an n-type polycrystalline Si film having a predetermined shape;
A high-resistance polyjunction consisting of a thin intrinsic polycrystalline Si film, ν, Si-low Si1, R2, is provided. The wiring layer 13 is connected to M O through contact holes 14 provided in the interlayer insulating film 12 and the gate insulating film 4, respectively.
S F E T Q 3. It is in contact with the source region 9 of Q4.

rl” type polycrystalline 5il 1%% which constitutes the wiring layer 13
The thickness of the wiring layer 13 is selected to be, for example, 1000 Å or more, and thereby the sheet resistance of the wiring layer 13 can be reduced to about 100 Ω/hole or less (see FIG. 5). Therefore, it is possible to prevent signal delay due to wiring resistance.

The film thickness of the intrinsic polycrystalline Si film constituting the high-resistance polycrystalline Si resistors R+ and R2 is smaller than the film thickness of the n-type polycrystalline Si film constituting the wiring layer 13.
The thickness is selected to be 00 Å or less. As a result, high resistance polycrystalline Si resistors R1 and R2 are maintained while keeping the resistance value of the wiring layer 13 low.
Since the resistance value of can be increased, Iss can be set to about 0.
It can be reduced to 5μ8 or less (see Figure 5). Furthermore, in the past, it was necessary to set the length of the high-resistance polycrystalline Si resistors R+ and R2 to 4 to 5 μm in order to obtain a sufficient resistance value, but according to this embodiment, the high-resistance polycrystalline Si resistor By increasing the resistance value by making R1 and R2 thinner, the length of these high resistance polycrystalline Si resistors R+ and R2 can be reduced to, for example, 2 to 4 μm. Therefore, since the area of the memory cell can be reduced by this amount, the integration density can be increased.

Furthermore, in the static RAM according to this embodiment, the wiring layer 13. An interlayer insulating film 15 such as a PSG film is provided to cover the high-resistance polycrystalline Si resistors R1, R2, etc., and on this interlayer insulating film 15, theta wires DL and (1) made of an Al film are provided. ing. These data lines D
L and DL are interlayer insulating film 12.15 and gate insulating film 4
M through contact holes 16 provided in
Drain region 10 of O5FE TQs, Qa
is in contact with. In FIG. 1A, the data lines DL and DL are shown by dashed-dotted lines to make the drawing easier to understand, and the interlayer interval '4*ll! of the second layer is shown. I15 was omitted.

Next, a method for manufacturing the static RAM according to the above embodiment will be explained. First, as shown in FIGS. 1A and 1B, the MOS FET Q I-Q 4 and the word line W
L, ground line SL, etc. are formed, and an interlayer insulating film 1 is formed on these.
2, a contact hole 14 is formed. Next, as shown in FIG. 2A, a relatively thick intrinsic polycrystalline Si film of about 500 A is formed on the interlayer insulating film 12.
After forming the film 17, a portion of the intrinsic polycrystalline Si film 17 corresponding to a high resistance polycrystalline Si resistor to be formed later is selectively etched away to form an opening 17a. Next, as shown in FIG. 2B, an intrinsic polycrystalline Si film 1B is formed which is about 500 times thinner than the high resistance polycrystalline Si resistor. Next, on this intrinsic polycrystalline S1 film, a mask layer 1 having a planar shape, for example, as shown in FIG.
9 is provided, by performing phosphorus diffusion, ion implantation, etc., to lower the resistance of the polycrystalline Si film 17.1B in the portion not covered by this mask layer 19. In the first step, this mask layer 19 is removed. After that, these polycrystalline Si films17.18
By patterning it into a predetermined shape, as shown in FIG. A low-resistance wiring layer 13 made of A and high-resistance polycrystalline s1 resistors R1 and R2 (only R1 is shown in FIG. 2C) made of an intrinsic polycrystalline Si film having a film thickness of, for example, 500 are formed. After this, as shown in FIGS. 1A and 1B, the interlayer 811Si15. A contact hole 16 and data lines DL and D are formed to complete the intended static RAM.

The above-mentioned high-resistance polycrystalline Si resistors R1 and R2 are made by first forming an intrinsic polycrystalline Si film 17, and then reducing the resistance of this intrinsic polycrystalline Si film 17 by phosphorus diffusion, etc., by removing a portion that will later become a resistor. , it is also possible to form it by etching the portion left with high resistance.

According to the manufacturing method described above, a static RAM having a small IsB and capable of high-speed operation can be manufactured by a simple process.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, as shown in FIG. 3, a thin intrinsic polycrystalline 5illQ18 and a thick n-type polycrystalline Si film 20 are provided on the first interlayer insulating film 12, and this n-type polycrystalline Si film 20 is partially removed. Then, a high resistance polycrystalline Si resistor is formed in only one layer of the intrinsic polycrystalline Si film 18, forming R2 (only R1 is shown in FIG. 3), and the intrinsic polycrystalline s
The JFH3 may be formed by two layers of the 1 film 18 and the RL' type polycrystalline Si film 20. Also, a high melting point metal silicide film may be used instead of the n° type polycrystalline s1 film 2o shown in FIG. The high-melting-point metal silicide film is partially removed, and high-resistance polycrystalline Si resistors R+ and R2 are formed from only one layer of the intrinsic polycrystalline Si film 18, and the intrinsic polycrystalline Si film 18 and The wiring layer 13 is formed by a two-layer film (polycide film) made of a high melting point metal silicide film.
It is also possible to configure

〔Effect of the invention〕

A brief explanation of the effects obtained by one representative invention among the inventions disclosed in this application is as follows.

That is, I ss can be reduced and high-speed operation can be achieved.

[Brief explanation of drawings]

1A and 1B are a plan view of a main part of a static RAM according to an embodiment of the present invention and a cross-sectional view taken along the line B-B, respectively. FIG. 3 is a cross-sectional view of a main part showing a modification of the present invention, and FIG. 4 is a high-resistance polycrystalline Si-loaded memory. FIG. 5 is a circuit diagram showing the circuit configuration of the cell, and FIG. 5 is a graph showing the relationship between the Isu measured by the present inventor and the sheet resistance of the wiring layer made of the mouth-shaped polycrystalline Si film and the polycrystalline Si film thickness. .

Claims (1)

[Scope of Claims] 1. In a static RAM having a high resistance polycrystalline Si load type memory cell in which a high resistance polycrystalline Si resistor made of an intrinsic polycrystalline Si film is connected to a wiring layer, the high resistance polycrystalline Si resistor is connected to a wiring layer. A static RAM characterized in that a resistor is made thinner than the wiring layer. 2. The static RA according to claim 1, wherein the wiring layer is made of an n^+ type polycrystalline Si film.
M. 3. The static RAM according to claim 1, wherein the wiring layer is made of a polycide film. 4. The static RAM according to claim 1, wherein the wiring layer is composed of an n^+ type polycrystalline Si film and an intrinsic polycrystalline Si film. 5. A patent characterized in that the thickness of the intrinsic polycrystalline Si film constituting the high-resistance polycrystalline Si resistor is 500 Å or less, and the thickness of the n^+ type polycrystalline Si film is 1000 Å or more. A static RAM according to claim 2 or 4.