JPH0669461A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To assure the operation of a RAM cell and facilitate manufacture of a more highly integrated S-RAM by a method wherein a barrier layer which prevents impurities from being diffused from the gate electrode part of a MOS transistor into a load resistor part is provided between the gate electrode and the load resistor as their connection part. CONSTITUTION:Field oxide films 102, gate oxide films 103, N<+>-type gate polycrystalline silicon layers 104 which are to be the gate electrodes of a transistor and N<+>-type diffused layers 105 which are to be the source and drain of the transistor are formed on a P-type silicon substrate 101. Then a contact hole is drilled in an insulating film 106 and a high resistance polycrystalline silicon layer 108 which is to be the load resistor is formed and connected to the N<+>-type gate polycrystalline silicon layer 104. A titanium nitride layer 107 is provided between the gate electrode 104 and the high resistance polycrystalline silicon layer 108 as their connection part. The titanium nitride film 107 functions as a barrier which prevents impurities from being diffused from the gate electrode 104 into the high resistance polycrystalline silicon layer 108 and avoids the decline of a resistance value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a high resistance load type static RAM.

[0002]

2. Description of the Related Art In recent years, CMOS and BiCMOS are provided with logic and static RAM (hereinafter referred to as SRAM).
The development of LSIs with mixed
As for the degree of integration of AM, more highly integrated ones are required. Conventionally, as a RAM cell configuration used for such an application, there is a high resistance load type cell as shown in FIG. In the figure, Q1 and Q2 are driver transistors, which are driven by using the high resistance of R1 and R2 as a load, and the logic is latched by positive feedback of two stages of inverters. Further, Q3 and Q4 control the reading and writing of the latched data as transfer gates.

In such a high resistance load type cell, the connection portion A between the transistors Q1 and Q2 and the load resistors R1 and R2 is realized by an element structure as shown in FIG. 3 in order to achieve high integration. . The figure shows a cross section of the element only in the vicinity of the connection portion of Q1, R1, and Q3.
A field oxide film 302 and a gate oxide film 303 are formed on top of this, gate polysilicon 304 to be the gate electrodes of Q1 and Q3 is formed, and an N ⁺ -type diffusion layer 305 to be the source and drain is formed. A connection hole is opened in the insulating film 306 and a high resistance polysilicon 307 is formed in a thickness of 100 to 200 n.
It is deposited to a film thickness of about m (nanometer) and patterned to form a load resistance.

By connecting the load resistor and the gate electrode in this way, higher integration can be achieved as compared with the case where each is connected by a wiring material.

[0005]

In this conventional cell structure, the load resistance is 10 ¹¹ in order to reduce the static current consumption.
Although it is necessary to use an ohmic material, if the resistance length is reduced as shown by the solid line in FIG. 5, the resistance value suddenly decreases from about 2 μm and the operation as a RAM cell cannot be guaranteed.

The cause of this is that impurities (eg, phosphorus) heavily doped to reduce the resistance of the gate polysilicon at the connection portion between the gate electrode and the high resistance polysilicon shown in FIG. This is because the resistance diffuses to the polysilicon side and the resistance decreases. This phenomenon is the same when tungsten polycide (= two-layer structure of N ⁺ type polysilicon + tungsten silicide) or the like is used as the gate electrode. Since the impurity diffusion in the silicide is fast, the high impurity concentration side (gate electrode) It cannot prevent diffusion to the low impurity concentration side (high resistance polysilicon). That is, there is a problem that the resistance length cannot be reduced to a certain extent or more to guarantee the cell operation.

[0007]

A high resistance load type static RAM cell of the present invention is a barrier layer for suppressing impurity diffusion from a gate electrode portion to a load resistance portion at a connection portion between a gate electrode of a MOS transistor and the load resistance. Is equipped with.

[0008]

1 is a sectional view showing a static RAM cell according to a first embodiment of the present invention, showing a connection portion A between a driver transistor and a load resistance shown in FIG. 4 and its vicinity. A field oxide film 102 and a gate oxide film 103 are formed on a P-type silicon substrate 101, and N ⁺ -type gate polysilicon 104 serving as a gate electrode of the transistors Q1 and Q3 (or Q2 and Q4) and N serving as a source and a drain are formed. ^{The +} -type diffusion layer 105 is formed, the insulating film 106 connection hole is formed on the diffusion layer 105, and the high-resistance polysilicon 108 serving as the load resistance R1 (or R2) is formed and connected. The difference from the cell is that a titanium nitride layer 107 is sandwiched between the connection portion of the gate electrode 104 and the high resistance polysilicon 108. The method for forming this layer is, for example, 300 nm
After depositing the insulating film 106 having a thickness of about 100 nm, the gate electrode 104
After forming a connection hole on the upper surface and forming titanium nitride with a film thickness of about 50 nm on the entire surface, a resist is applied to fill the connection hole, and the entire surface is etched back to remove the resist remaining in the connection hole. Such a method may be used.

This titanium nitride layer 107 is formed on the gate electrode 10.
4 acts as a barrier against impurity diffusion from the high resistance polysilicon 108 to the resistance length 2 as shown by the dotted line in FIG.
It is possible to prevent the resistance value from drastically decreasing when the thickness is less than μm.

FIG. 2 is a cell sectional view of the second embodiment of the present invention. 2, parts having the same functions as those in FIG. 1 are denoted by the same reference numerals. The second embodiment is different from the first embodiment shown in FIG. 1 in that titanium nitride 207 serving as a barrier layer is formed on the entire gate electrode 104. As a method of forming this structure, a method may be used in which a gate electrode material having a film thickness of about 300 nm is entirely deposited, titanium nitride is formed to a film thickness of about 50 nm on the entire surface, and the gate electrode 104 is simultaneously etched when the gate electrode 104 is patterned. Therefore, there is an advantage that an extra step such as etch back as in the case of FIG. 1 is not required.

As described above, according to the present invention, since the barrier layer for suppressing the impurity diffusion is provided at the connecting portion between the gate electrode and the high resistance polysilicon, the resistance value does not decrease sharply even if the resistance length is reduced. The operation of the RAM cell can be guaranteed, and as a result, it is possible to manufacture a highly integrated SRAM.

[Brief description of drawings]

FIG. 1 is a sectional view showing a memory cell according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a memory cell according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a conventional memory cell.

FIG. 4 is a circuit diagram of a high resistance load type RAM memory cell.

FIG. 5 is a diagram showing the resistance length dependency of the resistance value of high-resistance polysilicon.

[Explanation of symbols]

101, 301 P-type silicon substrate 102, 302 Field oxide film 103, 303 Gate oxide film 104, 304 Gate polysilicon 105, 305 N ⁺ type diffusion layer 106, 306 Insulating film 107, 207 Titanium nitride 108, 308 High resistance polysilicon

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/90 C 7514-4M

Claims (2)

[Claims] 1. A semiconductor integrated circuit device comprising: a cell portion of a high resistance load type static RAM, wherein a barrier layer is provided at a gate electrode of a MOS transistor and a load resistance connection portion. 2. The semiconductor integrated circuit device according to claim 1, wherein titanium nitride is used as the barrier layer.