JPH0210733A - Semiconductor device - Google Patents

Abstract

PURPOSE:To sandwich a field insulating film to prevent punching-through production between neighboring diffusion layers by making the impurity concentration of a part in the neighborhood of contact parts of a semiconductor film for forming gate wiring lower than that of the other part. CONSTITUTION:Contact parts C2, C'2 in which gate wiring G1, G'1 are directly connected to a semiconductor substrate 1 sandwich a field insulating film 2 to near and is formed. The impurity concentration of the part in the neighborhood of contact parts of polycrystalline Si films for forming G1, G'1 is made lower than the other parts. Therefore, the joining depth of diffusion layers formed by impurity diffusion of the polycrystalline Si film to the substrate 1 can be made shallow. Thereby punching-through production between the diffusion layers neared and formed by sandwiching the field insulating film can be prevented and the improvement of integrated density by the use of contacts can be contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, for example, a MOS state 47.
RAM (Random Access Mes+o
ry) is suitable for application.

(Summary of the Invention) The present invention provides a semiconductor device in which contact portions in which a gate wiring is directly connected to a semiconductor substrate are formed adjacent to each other across a field insulating film, in which the gate wiring is a semiconductor device containing impurities. The impurity concentration of a portion of the gate wiring adjacent to the contact portion is lower than the impurity concentration of other portions.Thereby, the gate wirings are formed close to each other with a field insulating film in between. High integration density can be achieved without causing punch-through between diffusion layers.

[Conventional technology]

In recent years, high-resistance polycrystalline silicon (Si) loaded static RAMs have become mainstream in MOS static RAMs. As shown in FIG. 2, the memory cell of this high-resistance polycrystalline Si loaded static RAM is composed of an inverter consisting of a high-resistance polycrystalline Si resistor R1 and a driver transistor T+, a high-resistance polycrystalline Si resistor R2, and a driver transistor T2. A flip-flop circuit in which the output of one of the two inverters is connected to the input of the other, and a switching transistor (access transistor) T3 for exchanging data with the outside of the cell.
, T4. Symbol WL is a word line, symbol DL, D
L is a data line. ■. , represents the power supply.

In the above-mentioned high-resistance polycrystalline Si-loaded static RAM, a so-called buried contact is used in which gate wiring etc. are brought into direct contact with the semiconductor substrate.
The integration density of memory cells has been improved by using contact memory. Specifically, this buried contact is used, for example, at the connection portion between the gate wiring forming the gate electrode of the driver transistor T shown in FIG. 2 and the source region (diffusion layer) of the switching transistor T4.

By the way, the material for this gate wiring is usually a polycrystalline Si film doped with impurities, or a polycrystalline Si film doped with impurities such as tungsten silicide (W).
S iz ) and molybdenum silicide (M.

A so-called polycide film, in which high-melting point metal silicide films such as 5 inch) are stacked, is used. Therefore, in the buried contact part described above, the polycrystalline S doped with this impurity is
The structure is such that the t film is in direct contact with the diffusion layer.

[Problem to be solved by the invention]

According to studies by the present inventors, the above-mentioned high-resistance polycrystalline Si loaded static RAM using buried contacts has the following problems. This problem will be explained below by taking as an example a case in which a gate wiring is formed of a polycrystalline Si film doped with an n-type impurity such as phosphorus (P).

In the conventional manufacturing method of a high-resistance polycrystalline Si loaded static RAM, the steps up to the formation of the source region and drain region of the transistor are outlined as follows. That is, first, a field insulating film is formed on the surface of a semiconductor substrate to isolate elements, and then a gate insulating film is formed on the surface of an active region surrounded by this field insulating film. next,
Predetermined portions of the gate insulating film and the field insulating film are selectively etched away to partially expose the surface of the semiconductor substrate in the buried contact portion. Next, after forming a polycrystalline Si film on the entire surface, this polycrystalline Si film is
Dope the film with P. During the heat treatment for this diffusion, P diffuses into the semiconductor substrate from the polycrystalline Si film directly in contact with the surface of the semiconductor substrate, thereby forming an n° type diffusion layer in the semiconductor substrate. Next, this polycrystalline Si film is patterned by etching to form gate wiring. Thereafter, impurity ions for forming source and drain regions are implanted into the semiconductor substrate using this gate wiring as a mask. This forms n° type source and drain regions. in fact,
The entirety of these source and drain regions formed by ion implantation and the diffusion layer previously formed by impurity diffusion from the polycrystalline Si film becomes the source and drain regions.

For example, if we consider the source region of the switching transistor T4 that is in contact with the gate wiring constituting the gate electrode of the driver transistor T shown in FIG. are formed close to each other. The junction depth in the portion of this source region that is in contact with the gate wiring is determined only by impurity diffusion from the polycrystalline St film. On the other hand, the junction depth in the portion of this source region that is not in contact with the gate wiring is polycrystalline St.
Deeper than either impurity diffusion from the film or ion implantation (
Determined by what is diffused.

By the way, in actual process design, it is preferable to design the junction depth determined by ion implantation for forming the source region and the drain region to be the deepest. This is because, from the viewpoint of improving integration density, it is desirable not to be constrained by factors other than ion implantation for forming source and drain regions. This is because, in the case of the source region mentioned above, the junction depth of this source region is determined only by ion implantation, and the junction depth determined by this is the portion of this source region that is in contact with the gate wiring. This means that the bonding depth is deeper than the bonding depth at . In this case, if the junction depth of the source region in the part where the gate wiring is in contact is deeper than the junction depth of the source region in the part where the gate wiring is not in contact, the source region in the part where the gate wiring is not in contact is The junction depth is also equal to or greater than the junction depth of the source region in the portion where the gate wiring is in contact. In such a case, the above-mentioned source regions that are formed close to each other with a field insulating film in between between adjacent memory cells may come close to each other, and as a result, punch-through may occur.

Therefore, an object of the present invention is to provide a semiconductor device that can achieve high integration density without causing punch-through between diffusion layers formed close to each other with a field insulating film in between.

[Means to solve the problem]

In order to solve the above problems, the present invention provides gate wiring (G+
, Gz, G+') are directly connected to the semiconductor substrate (1) in a semiconductor device in which contact portions (Cz, G3, Cz') are formed close to each other with a field insulating film (2) in between. Gate wiring (G, ,G
2, G, ') is composed of a semiconductor film containing impurities, and the gate wirings CG+, Gt, G+'
) contact parts (Cz, G3, Cz'
) is lower than the impurity concentration in other parts.

[Effect]

According to the above means, the gate wiring (G, , Gz, G
+') of the semiconductor film constituting the contact part (c,
, G3, ct') is lower than the impurity concentration in other parts, the junction depth of the diffusion layer formed by impurity diffusion from this semiconductor film into the semiconductor substrate becomes shallow. . Therefore, punch-through is prevented from occurring between the diffusion layers formed close to each other with the field insulating film in between.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to a high resistance polycrystalline Si loaded static RAM.

FIG. 1A shows a planar structure of a high-resistance polycrystalline Si-loaded static RAM according to an embodiment of the present invention, and FIG. 1B shows a cross-sectional view taken along line BB in FIG. 1A. The equivalent circuit of the memory cell of this high resistance polycrystalline Si loaded static RAM is shown in FIG. In FIG. 1A, one memory cell is indicated by a two-dot chain line.

As shown in FIGS. 1A and 1B, in the high resistance polycrystalline Si loaded static RAM according to this embodiment,
A field insulating film 2, such as a 5i01 film, is selectively formed on the surface of a semiconductor substrate 10, such as a p-type St substrate, thereby providing isolation between elements. A gate insulating film 3 such as a SiOg film is formed on the surface of the active region surrounded by the field insulating film 2, and on this gate insulating film 3 and the field insulating film 2, a word line WL and a gate electrode G+ are formed. , Gz are formed. These word lines WL and gate electrodes G7 and Gt are
For example, it is composed of a first-layer polycrystalline St film doped with an n-type impurity such as P or arsenic (As), or a polycide film in which a refractory metal silicide film is superimposed on this polycrystalline Si film.

On the other hand, in the active region surrounded by the field insulating film 2, for example, n' type source regions 4 to 7 and drain regions 8 to 11 are formed. Of these, the source region 4 and drain region 8 are formed in a self-aligned manner with respect to the gate electrode G1, and the source region 5 and drain region 9 are formed in a self-aligned manner with respect to the gate electrode G2. Also, source region 6.7 and drain region 10.11
are formed in self-alignment with the word line WL. Note that the source region 6 and drain region 8 are integrally formed. n-channel MI configured by the gate electrode Gl, source region 4 and drain region 8
A driver transistor T is constituted by an SFET. Similarly, the n-channel MISFE is configured by the gate electrode Gt, the source region 5, and the drain region 9.
T constitutes a driver transistor T2, and an n-channel MISFET constituted by the word line WL, source region 6, and drain region IO constitutes a switching transistor 1''. Switching transistor 1 is formed by an n-channel MISFET consisting of
゛4 is configured.

Symbols C and -C indicate contact holes formed in the gate insulating film 3 and field insulating film 2, and are for buried contacts. One end of the gate electrode G1 is connected to the drain region 9 through this contact hole C1.
The other end is in contact with the source region 7 through a contact hole C2. Also,
The gate electrode G2 is in contact with the source region 6 through the contact hole C1. Reference numeral 12 denotes a ground line (for example, made of a first layer of polycrystalline Si film doped with n-type impurities such as P or As, or a polycide film in which a refractory metal silicide film is layered on this polycrystalline Si film).
source line). This ground line 12 is in contact with the source region 4 through the contact hole C4, and is also in contact with the source region 5 through the contact hole C2.

In this embodiment, the impurity concentration of the portion of the polycrystalline Si film constituting the gate electrodes G, G, word line WL, and ground line 12 adjacent to the buried contact portion is, for example, 5X10"cm-" (approximately 1 Ω/hole in terms of sheet resistance), and the impurity concentration in other portions is, for example, about 10 cm − (approximately 50 Ω/hole in terms of sheet resistance).

Reference numeral 13 indicates a glabellar insulating film such as a Sin film. Contact holes C&, C' are provided in this insulating film 13 between the eyebrows.
F is formed. Further, on this glabellar insulating film 13, a wiring 14 for supplying the power supply voltage VCC is formed.
This wiring 14 is connected to the source region 6 through the contact hole C6 and to the contact hole C? It is in contact with the source region 7 through. This wiring 1
4, high resistance polycrystalline Si resistors R, , R, are formed in the middle. These wiring lines 14 and high-resistance polycrystalline Si resistors R, , R, are formed of, for example, a second layer of polycrystalline Si film. The polycrystalline Si film constituting this wiring 14 is doped with an n-type impurity such as P at a high concentration, while the polycrystalline Si film constituting the high resistance polycrystalline Si resistor RR2 is undoped.

Reference numeral 15 indicates a second interlayer insulating film such as a 5iOz film. On this glabellar insulation 85115, data lines DL and FF (only DL is shown in FIG. 1B) made of, for example, an aluminum (AI) film are formed.

Symbols C, , C, indicate contact holes formed in the interlayer insulating film 15, 13 and the gate insulating film 3. The data line DL is in contact with the drain region IO through this contact hole C1, and the data line T is in contact with the drain region 11 through this contact hole C3.

Note that corresponding portions of other memory cells adjacent to one memory cell shown in FIGS. 1A and 1B are indicated by reference numerals appended with "r'".

Next, an example of a method for manufacturing the high-resistance polycrystalline St-loaded static RAM according to this embodiment configured as described above will be described.

As shown in FIGS. 1A and 1B, first, a semiconductor substrate 1
After selectively thermally oxidizing the surface of the field insulating film 2 to form a field insulating film 2, the surface of the active region surrounded by the field insulating film 2 is thermally oxidized to form a gate insulating film 3. Next, predetermined portions of the gate insulating film 3 and field insulating film 2 are removed by etching to form contact holes C1-c,,c,',Ct'' for buried contacts.Next, for example, by CVD method, After forming a polycrystalline Si film on the entire surface,
For example, an n-type impurity such as P or As is diffused over the entire surface of this polycrystalline Si film to form a
During this diffusion, the n-type impurity in the polycrystalline Si film diffuses into the semiconductor substrate 1, and as a result, the n'-type impurity in the semiconductor substrate 1 is doped. A diffusion layer (portion indicated by a broken line in FIG. 1B) is formed. Note that ion implantation can also be used instead of this diffusion.

Thereafter, the surface of the portion of the impurity-doped polycrystalline Si film corresponding to the buried contact portion is covered with, for example, a photoresist (not shown), and the polycrystalline Si film is coated with this photoresist as a mask. For example, P or As
For example, if an n-type impurity such as
Ion implantation is performed under conditions of approximately Ca1-''. As a result, the impurity concentration in the portion of this polycrystalline Si film other than the portion adjacent to the buried contact portion becomes approximately 10''C11-'', resulting in low resistance. .

Thereafter, this polycrystalline Si film is patterned by etching to form gate electrodes Gl % Gt % word lines WL
and a ground line 12. Note that when these gate electrodes Gl, G, , word line WL, and ground line 12 are formed of a polycide film, the above-mentioned patterning is performed after forming a refractory metal silicide film on the above-mentioned polycrystalline Si film. I do. Since this etching is normally performed slightly over-etching, the surface of the semiconductor substrate 1 is also slightly etched (see FIG. 1B).

Next, these gate electrodes G, , G and word line W
Using L as a mask, ions are implanted to form source and drain regions into the active region surrounded by the field insulating film 2 using n-type impurities such as As. Due to impurity diffusion from the polycrystalline Si film, source regions 4 to 7 and drain regions 8 to
11 is formed.

Next, after forming an interlayer insulating film 13 over the entire surface by, for example, the CVD method, a predetermined portion of this glabellar insulating film 13 is removed by etching to form contact holes C4, C? , C? ' to form. Next, after forming a second layer of polycrystalline Si film on the entire surface by, for example, the CVD method, the surface of the portion of this polycrystalline Si film that will later become high resistance polycrystalline St, low resistance, R, □ Cover with a film or photoresist, and using this as a mask, the polycrystalline 5iBIl is doped with an n-type impurity such as P or As at a high concentration by ion implantation or the like. Thereafter, this polycrystalline SiM is patterned by etching to form a wiring 14 and high resistance polycrystalline Si resistors R9 and Rx connected to this wiring 14. next,
For example, after forming the eyebrow insulation [15] on the entire surface by CVD method, predetermined portions of the interlayer insulation film 15, the interlayer insulation film 13, and the gate insulation film 2 are removed by etching to form contact holes C, , C9, and C9'. Next, for example, an Al film is formed on the entire surface by, for example, a vapor deposition method or a sputtering method, and this Al film is patterned by etching to form data lines DL, DL. As a result, the desired high-resistance polycrystalline Si-loaded static RAM is completed.

As can be seen from the above, in this example, the impurity concentration in the portion of the polycrystalline Si film constituting the gate electrodes G+, Gt, and Gt' adjacent to the buried contact portion is low; From Si film to semiconductor substrate
The junction depth of the diffusion layer formed by diffusion of impurities into the layer can be made shallow (see FIG. 1B). Therefore, the junction depth of the source regions 7 and 7' can be determined only by ion implantation for forming the source and drain regions, and the junction depth of the diffusion layer formed by impurity diffusion from the polycrystalline Si film described above. It is possible to reliably prevent the junction depth from becoming deeper than the junction depth determined by this ion implantation. As a result, it is possible to prevent punch-through between the source regions 7 and 7' formed close to each other with the field insulating film 2 in between between adjacent memory cells.

That is, since punch-through does not occur even when a buried contact is used, it is possible to improve the integration density by using this buried contact.

Moreover, since the impurity concentration in the polycrystalline Si film constituting the gate electrodes Gl, Gt, the word line WL, and the ground line 12 except for the portion adjacent to the buried contact portion is sufficiently high, the wiring resistance is low. Therefore, when these gate electrodes G, , G2, word line WL, and ground line 12 are formed of a polycide film, there are the following advantages. In other words, when the impurity concentration of the polycrystalline Si film constituting this polycide film is low, a carrier-deficient portion is formed near the interface between the polycrystalline Si film and the high melting point metal silicide film, and as a result, this polycrystalline Si film is depleted in carriers. Problems arise, such as deterioration of ohmic properties between the Si film and the high melting point metal silicide film, and a decrease in the apparent capacitance of the gate insulating film, resulting in a decrease in the transconductance gm of the FET.

However, in this embodiment, these gate electrodes G as described above.

, G2, the word line WL, and the ground line 12, except for the portion adjacent to the buried contact portion, the impurity concentration is sufficiently high, so that such a problem does not occur. Therefore, the effect of lowering the resistance of the gate electrodes G, G2, word line WL, and ground *12 by using the polycide film can be sufficiently obtained, so that F E 'I
It is possible to improve the driving ability of ' and reduce the propagation delay time t□.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, it is also possible to use other types of semiconductor films instead of the polycrystalline Si films that constitute the gate electrodes G, , Q, , the word line WL, and the ground line 12.

Further, in the above embodiment, the case where the present invention is applied to a high-resistance polycrystalline Si loaded static RAM is described, but the present invention can be applied to various semiconductor devices using buried contacts. be. For example, the present invention can also be applied to a logic IC using an n-channel enhancement type/day 7' IJ-John type MOS transistor using buried contacts.

〔Effect of the invention〕

As described above, according to the present invention, the gate wiring is formed of a semiconductor film containing impurities, and the impurity concentration of the portion of the gate wiring adjacent to the contact portion is lower than the impurity concentration of other portions. Therefore, high integration density can be achieved without causing punch-through between the diffusion layers formed close to each other with the field insulating film in between.

[Brief explanation of the drawing]

FIG. 1A is a plan view showing a high-resistance polycrystalline Si-loaded static RAM according to an embodiment of the present invention, and FIG.
FIG. 2 is a cross-sectional view taken along the line BB in FIG. Explanation of main symbols in the drawings: Semiconductor substrate, 2: Field insulating film, 4-7: Source region, 8-11 Drain region, 13.15:
Interlayer insulating film, C2-C,,C. C2: Contact hole for buried contact, WL:
Word line, G+, G+, Gz: Gate electrode, DL, DL', DL: Data line, TI, T
z, TI: driver transistor, T,..., T4
, 'r'a' switching transistor, R1, R2
: High resistance polycrystalline silicon resistor. "i 11fi A*B-B line ahl:ili Fig.1

Claims (1)

[Claims] In a semiconductor device in which contact portions in which a gate wiring is directly connected to a semiconductor substrate are formed close to each other across a field insulating film, the gate wiring is formed of a semiconductor film containing impurities, and the gate wiring is A semiconductor device characterized in that an impurity concentration in a portion adjacent to the contact portion is lower than an impurity concentration in other portions.