JPH09129754A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method thereof, which prevent the formation of parasitic resistance at a node contact part and the deterioration of the pressure resistance of a TFT gate insulating film in an SRAM memory, wherein an upper-gate P-channel TFT is made to be a load element. SOLUTION: The connection of the gate electrode of a drive N-channel MOS transistor, an N-type diffused layer, a high-concentration P-type polycrystal silicon region, which is a TFT drain region, and a TFT gate electrode is performed by embedded electrodes 18a and 18b formed in node contact holes 17a and 17b. A TFT gate electrode 15b is arranged so that the electrode 15b is overlapped with the node contact hole 15b and does not protrude to the side of the TFT gate electrode 15a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a static random access memory (SRAM) having a P-channel thin film transistor (TFT) as a load MOS transistor.
The present invention relates to a cell structure and a manufacturing method.

[0002]

2. Description of the Related Art At present, in the SRAM memory cell, a system using a high resistance element as a load element has become mainstream because it is advantageous for high integration. However, as miniaturization and voltage reduction progress, in order to ensure stability against leakage current, noise, or soft error due to α-rays, a method using a P-channel TFT as a load element has become important.

Referring to FIG. 6, which is an equivalent circuit diagram of an SRAM memory cell, an SRAM memory cell having a P-channel MOS transistor as a load element is as follows.

This memory cell comprises six MOS transistors. For example, a pair of information transfer MOSFETs, ie, two transfer N-channel MOS transistors (T
T1, TT2) and a pair of driving MOSFETs, ie, 2
Drive N-channel MOS transistors (TD1, T
D2) and two load P-channel MOS transistors (TL1, TL2). These six MOS
The transistors are connected as follows. The first inverter composed of TD1 and TL1 and the second inverter composed of TD2 and TL2 are cross-connected at two connection points (N1, N2). The N-type source regions of TD1 and TD2 and the P-type source regions of TL1 and TL2 are connected to a ground line applied to Vss and a power supply line applied to Vcc, respectively.
The gate electrodes of TT1 and TT2 are one word line WL.
Source regions of TT1 and TT2 are connected to paired bit lines BL1 and BL2, respectively,
The N-type drain regions of T1 and TT2 are respectively N
1, N2.

When such a memory cell is formed, six MOS transistors (TT1, TT2, TD1, TD
2, TL1 and TL2) are formed on the same plane of the silicon substrate, and are 1.5 to 2 times larger than the high resistance load type memory cell.
This requires twice the cell area, and is not suitable for high integration.
However, four N-channel MOS transistors (TT1,
TT2, TD1, TD2) are formed on a silicon substrate, and two P-channel MOS transistors (TL1, T
If L2) is formed of a pair of load thin film transistors, that is, a pair of TFTs, and stacked above TT1, TT2, TD1, and TD2, the cell area becomes the same as that of the high-resistance load type, and high integration can be achieved. Realize.

At present, an SRAM memory cell using an upper gate type TFT as a load element, in which a gate electrode of the TFT is provided above a channel portion, has become important. The major reason is that the source / drain regions of the TFT can be formed in a self-aligned manner with respect to the gate electrode.

On the other hand, in the case of a lower gate type TFT in which the gate electrode of the TFT is below the channel portion, the above-mentioned source / drain cannot be formed in a self-aligned manner with respect to the gate electrode, which is not suitable for miniaturization of a memory cell. Come.

[0008] Such techniques are described, for example, in 1991-Symposium-On-VSL-Technology-Digest-of-Technical Papers,
Pages 23-24 (1991 Symposium o)
n VLSI Technology Digest
of Technical Papers pp. 23
−24).

FIG. 6 is an equivalent circuit diagram of an SRAM memory cell having a P-channel MOS transistor as a load element, and FIG. 7 is a schematic sectional view of the SRAM memory cell.
A conventional technique reported in the literature will be described with reference to FIG.

Although the above document does not show a plan view of the memory cell, inferring from the prior art, FIG. 7 shows that the bit line BL including one of the connection points N1 and N2 in FIG.
1 is a cross-sectional view in the direction parallel to BL2, and is considered to have a substantially symmetric structure between a cross section including N1 and a cross section including N2. Therefore, here, FIG. 7 is described as a cross section in the direction parallel to the bit line BL1 including N1.

Regarding the sectional structure including the connection point N2,
Transfer N-channel MOS transistors TT1, TT2,
Driving N-channel MOS transistors TD1, TD2,
The connection points N1 and N2 and the bit lines BL1 and BL2 may be replaced with each other.

As shown in FIG. 7, on a surface of a silicon substrate 101, an element isolation oxide film 102 and a gate oxide film 10 are formed.
3 are provided. Then, a driving gate electrode 104 and a transfer gate electrode 105 are formed on the gate oxide film 103. Further, in the element formation region on the surface of the silicon substrate 101, N-type diffusion layers 106a and 106b are self-aligned with the element isolation oxide film 102 and the transfer gate electrode 105.
Is provided.

In this manner, the driving gate electrode 10
4. The driving N-channel MOS transistor TD2 is composed of the gate oxide film 103 and an N-type diffusion layer (not shown) arranged in a direction perpendicular to the plane of the drawing with the driving gate electrode 104 interposed therebetween. Also, the transfer gate electrode 10
5, the N-type diffusion layer 106a (N-type drain region) and the N-type diffusion layer 106b (N-type source region) constitute a transfer N-channel MOS transistor TT1. Here, the transfer gate electrode 105 also serves as the word line WL,
The type diffusion layer 106a also serves as a drain region of a driving N-channel MOS transistor TD1 not shown in the figure.

A ground line 108 having a polycide structure is provided on these N-channel MOS transistors via a first interlayer insulating film 107. Although not shown, this ground line 108 is used for grounding. N-channel MOS transistors TD1, T2
It is connected to the N-type diffusion layer serving as the source of D2. The surface of the first interlayer insulating film 107 including the ground line 108 is covered with the second interlayer insulating film 109.

The first interlayer insulating film 107 and the second interlayer insulating film 109 have connection contact holes 11 reaching both on the drive gate electrode 104 and on the N-type diffusion layer 106a.
Bit line contact holes 111 reaching the 0 and N type diffusion layers 106b are opened, and the insides of these connection contact holes 110 and bit line contact holes 111 are made of N-type doped polycrystalline silicon. Embedded electrodes 112 and 113 are formed. In this manner, the driving gate electrode 104 and the N-type diffusion layer 106a are connected to the connection contact hole 11 through the buried electrode 112.
0 Internally connected.

A titanium silicide layer is formed on the top of the buried electrode 112 in order to eliminate a PN diode parasitically formed between the P-type drain region of the TFT and the N-type buried electrode 112. 114 are formed. At the same time, a titanium silicide layer 115 is also formed on the buried electrode 113.

Then, an upper gate type load P-channel TFT is formed on the surface of the second interlayer insulating film 109. That is, a polycrystalline silicon film pattern is formed on the second interlayer insulating film 109, and this polycrystalline silicon film pattern becomes a high-concentration P-type polycrystalline silicon region 116 serving as a source region of the TFT and a channel region. N-type polysilicon region 117, high-concentration P-type polysilicon region 118 serving as a drain region, LDD (Lightly
Low-concentration P-type polycrystalline silicon regions 119a and 119b to be Doped Drain regions are formed. On the TFT gate insulating film 120, a power supply wiring 121 made of a P-type polycrystalline silicon film and TFT gate electrodes 122a and 122b are formed. Power supply wiring 12
1. The TFT gate electrode 122b is connected to the high-concentration P-type polysilicon region 11 through the contact hole.
6 and 118 are connected.

In this manner, the TFT gate electrode 12
2a, high-concentration P-type polysilicon region 116, low-concentration P
A load P-channel TFT TL1 is composed of the type polycrystalline silicon region 119a, the N type polycrystalline silicon region 117, the low concentration polycrystalline silicon region 119b, and the high concentration P type polycrystalline silicon region 118. Gate electrode 1 for TFT
22b is a gate electrode of the load P-channel TFT TL2.

Further, a protective insulating film 123 is deposited,
An interlayer insulating film 124 is formed, and a bit line 125 is provided. Here, the bit line 125 is connected to the titanium silicide layer 115 via the contact hole.

Next, a conventional manufacturing method will be briefly described with reference to FIG. FIG. 8 is a sectional view of the SRAM memory cell portion in the order of the manufacturing process.

As shown in FIG. 8A, an element isolation oxide film 102 is formed in an element isolation region on the surface of a P-type silicon substrate 101, and a gate oxide film 103 is formed in an element formation region. You. An N-type polycrystalline silicon film and a tungsten silicide film are sequentially formed on the entire surface, and these laminated films are patterned to form a driving gate electrode 10.
4. The transfer gate electrode 105 is formed. N-type diffusion layers 106a, 1a are formed on the surface of the P-type silicon substrate 101 by ion implantation of N-type impurities using the element isolation oxide film 102, the driving gate electrode 104, and the transfer 105 as a mask.
06b is formed.

Next, a first interlayer insulating film 107 is formed on the entire surface, and after opening a ground contact (not shown), an N-type polycrystalline silicon film and a tungsten silicide film are sequentially formed on the entire surface. You. These laminated films are patterned to form the ground line 108.

Next, a second interlayer insulating film 109 having a flat surface is formed on the entire surface, and the first and second interlayer insulating films 10 are formed.
9, 107, and reaches both the drive gate electrode 104 and the N-type diffusion layer 106a.
A bit line contact hole 111 reaching the 0, N type diffusion layer 106b is opened. This connection contact hole 110,
The inside of the bit line contact hole 111 is filled with N-type polycrystalline silicon, and buried electrodes 112 and 113 are formed. Here, by forming titanium on the entire surface and performing heat treatment, titanium silicide layers 114 and 115 are formed only on the buried electrodes 112 and 113 in a self-aligned manner.

Next, a polycrystalline silicon film containing an N-type impurity is formed on the entire surface and patterned to form an N-type polycrystalline silicon region 117. On top of that, TF
A gate insulating film for T is formed, and a P-type polycrystalline silicon film is formed on the entire surface after the opening of the contact hole. This is patterned to form a power supply line 121 and TFT gate electrodes 122a and 122b (FIG. 8A).

Here, BF ₂ ions, which are P-type impurities, are implanted into the entire surface at an area density of about 3 × 10 ¹³ cm ⁻² ,
Using the TFT gate electrode 122a as a mask, the low-concentration P-type polysilicon regions 119'a and 119 'are self-aligned.
b is formed (FIG. 8B).

Next, a protective insulating film 123 for forming the LDD structure is formed on the entire surface, and BF which is a P-type impurity is formed on the entire surface.
_By implanting _two ions at an area density of about 1 × 10 ¹⁵ cm ⁻² , the high-concentration P-type polysilicon region 116,
118 is formed. At this time, the power supply wiring 121, TF
In the portion covered with the T gate electrode 122b, regions 116 'and 118' which are masked and do not have impurity implantation are left, but the power supply line 121, the TFT gate electrode 122b
Is made of a P-type polycrystalline silicon film. If a sufficient heat treatment is applied thereafter, the P-type impurities are diffused through the contact holes, so that the region 11 without the impurity implantation is formed.
It is assumed that 6 ′ and 118 ′ disappear (FIG. 8 (c)).

Next, a third interlayer insulating film 124 is formed on the entire surface, and the third interlayer insulating film 124, the protective insulating film 123, and the TFT
A contact hole penetrating through the gate insulating film 120 for use and reaching the titanium silicide layer 115 is opened, and finally the bit line 125 is formed, whereby the structure of FIG. 7 is completed.

[0028]

In the above-mentioned prior art, as shown in FIG.
Regions 116 'and 118' without impurity implantation are formed below the FT gate electrode 122b. In order to form the LDD structure in a self-aligned manner, the power supply wiring 121 and the TF
At the end of the T gate electrode 122b, low-concentration P-type polycrystalline regions 119'a and 119'b are also formed. If these are left, they act as a series resistor for the load P-channel TFT, which significantly reduces the current supply capability of the TFT. For example, when an impurity is not implanted, a polycrystalline silicon film has an LDD of about 10 ¹² Ω / □ per unit area.
The low concentration polycrystalline silicon film used for the region is 10
^It shows a very high layer resistance of about ⁶ Ω / □. In order to remove these, it is necessary to diffuse the P-type impurity by a sufficient heat treatment as described above. However, performing this sufficient heat treatment is required for the following three reasons.
It becomes difficult to apply to AM.

First, an N-channel and a P-channel MOS transistor are formed under the load P-channel TFT (on the surface of the silicon substrate).
The channel and P-channel MOS transistors have been subjected to a heat treatment in the step of planarizing the interlayer insulating film even before the formation of the load P-channel TFT. Therefore, performing a high-temperature and long-time heat treatment after forming a TFT is difficult for these fine MOSs.
There is a high risk that the characteristics of the transistor will be significantly degraded by the short channel effect.

Secondly, in the case of forming the LDD structure, in order to effectively relax the electric field in the drain portion and reduce the leak current of the TFT, the high concentration P which becomes the drain region is formed.
Type polycrystalline silicon region 118 corresponds to TFT gate electrode 1.
It is desirable to be offset from 22a. This is because if the high-concentration P-type polycrystalline silicon region 118 overlaps with the TFT gate electrode 122a, the drain electric field becomes stronger due to the influence of the gate electric field. For this purpose, it is desirable to minimize the lateral diffusion of the P-type impurity in the high-concentration P-type polycrystalline silicon region 118, so that a high-temperature and long-time heat treatment should be avoided.

Third, titanium silicide layers 114 and 115 are formed above the buried electrodes 112 and 113. The titanium silicide layers 114 and 115 are formed.
When a high-temperature, long-time heat treatment is applied to the film, agglomeration of the film occurs, and the resistance rapidly increases.

Therefore, in the prior art, the regions 116 'and 118' where no impurity is implanted and the low-concentration P-type polycrystalline silicon regions 119'a and 119'b tend to remain, increasing the parasitic resistance and increasing the load. There is a problem that the current supply capability of the P-channel TFT is significantly reduced.

In the prior art, when the above-mentioned contact hole protrudes from the power supply line 121 or the TFT gate electrode 122b, when the power supply line 121 and the TFT gate electrodes 122a and 122b are patterned.
Since the etching also etches the polycrystalline silicon film serving as the base of the TFT, anisotropic dry etching is required at the time of opening the contact hole.
After that, the photoresist is removed by oxygen plasma, or a cleaning process using ammonia, sulfuric acid, or the like is performed. Therefore, a natural oxide film is formed in the contact hole.
1. The conduction between the TFT gate electrode 122b and the high-concentration P-type polycrystalline silicon regions 116 and 118 becomes impossible. In order to prevent this, light oxide film etching with diluted hydrofluoric acid must be performed as a pretreatment for forming the polycrystalline silicon. For this reason, the TFT gate insulating film 120 is locally thinned, and the gate insulating film is thinned. However, there is also a problem that the breakdown voltage failure easily occurs.

The cause of these problems lies in the manufacturing method, which is inseparable from the structure of the semiconductor memory device.

An object of the present invention is to provide an SRAM memory cell using an upper gate P-channel TFT as a load element, in which a high series resistance is not formed near the connection points (N1, N2 in FIG. 6), and the gate insulation of the TFT is prevented. An object of the present invention is to provide a structure and a manufacturing method in which film breakdown voltage failure does not extremely increase.

[0036]

According to the present invention, there is provided a semiconductor memory device comprising a pair of information transfer M formed on a surface of a semiconductor substrate.
In a static memory cell formed by an OSFET, a pair of driving MOSFETs and a pair of load thin film transistors constituting a flip-flop circuit,
A first N-type source region connected to the ground line, the first N-type
A first driving N formed on a surface of a silicon substrate, comprising a drain region of a type, a gate oxide film, and a first gate electrode.
A channel MOS transistor, a second N-type source region connected to a ground line, a second N-type drain region, the gate oxide film, and a second gate electrode, provided on the surface of the silicon substrate. Second drive N-channel MO
An S transistor, a third N-type source region connected to one of the pair of bit lines, a third N-type drain region connected to the first N-type drain region, the gate oxide film, And a third gate electrode connected to the word line, a first transfer N-channel MOS transistor provided on the surface of the silicon substrate, and a fourth N-type MOS transistor connected to the other of the pair of bit lines. And a fourth N-type drain region connected to the second N-type drain region, the gate oxide film, and a fourth gate electrode connected to the word line. And a second transfer N-channel MOS transistor provided on the surface thereof, wherein the first and second drive N-channel MOS transistors are provided.
A polycrystalline silicon film having a first interlayer insulating film covering the surface of the S transistor and the first and second transfer N-channel MOS transistors and provided on a surface of the second interlayer insulating film covering the ground line; A first polycrystalline silicon film pattern comprising a first P-type source region, a first channel region and a first P-type drain region connected to a power supply line; and the polycrystalline silicon film And a second polycrystalline silicon film pattern comprising a second P-type source region, a second channel region, and a second P-type drain region connected to the power supply line; A gate insulating film provided on the surface of the second interlayer insulating film, covering the surface of the second polycrystalline silicon film pattern, and covering the first channel region via the gate insulating film; P-shaped dray Has a portion extending over the region,
A fifth gate electrode formed on the surface of the gate insulating film; and a portion that covers the second channel region via the gate insulating film and extends over the first P-type drain region. A sixth gate electrode formed on a surface of the gate insulating film, the fifth gate electrode, the gate insulating film, the first P-type source region, the first
A first P-channel thin-film transistor for load comprising a channel region of the first type and the first P-type drain region; a sixth gate electrode; the gate insulating film;
A second load P-channel thin-film transistor comprising a source region of the same type, the second channel region, and the second drain region of the second P-type. A third interlayer insulating film covering the third interlayer insulating film, the sixth gate electrode, the gate insulating film, the first P-type drain region, the second and first interlayer insulating films, A first node contact hole penetrating the gate oxide film and reaching the second gate electrode or the first N-type drain region;
The third interlayer insulating film, the fifth gate electrode, the gate insulating film, the second P-type drain region, the second
And a second node contact hole penetrating through the first interlayer insulating film and the gate oxide film to reach the first gate electrode or the second N-type drain region; and A conductive first buried electrode formed inside the contact hole, and a conductive second buried electrode formed inside the second node contact hole; The second gate electrode or the first N-type drain region, the first P-type drain region, and the sixth gate electrode are connected to each other by one embedded electrode, and the second embedded electrode is First
Gate electrode or second N-type drain region, the second P-type drain region, and the fifth gate electrode are connected to each other, and in the vicinity of the first node contact hole, The gate electrode of No. 6 overlaps with the first node contact hole and is arranged so as not to have a protruding portion on the side of the fifth gate electrode, and in the vicinity of the second node contact hole, The fifth gate electrode is arranged so as to overlap with the second node contact hole and not to have a protruding portion on the side of the sixth gate electrode. Have.

The semiconductor memory device of the present invention also has a structure characterized in that the first and second buried electrodes are made of a high melting point metal film or an alloy film containing a high melting point metal.

Further, in the semiconductor memory device according to the present invention, the first and second P-channel thin film transistors for load may include:
A low concentration P between at least the drain region and the channel region.
There is also a structure characterized by having a mold region.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, an element isolation oxide film and a gate oxide film are formed in an element isolation region and an element formation region on the surface of a P-type silicon substrate, respectively. First N on the surface of the silicon substrate
A first driving N-channel MOS transistor including a first source region, a first N-type drain region, the gate oxide film, and a first gate electrode; a second N-type source region; A second driving N-channel MOS transistor including a second N-type drain region, the gate oxide film, and a second gate electrode; a third N-type source region; A first transfer N-channel MOS transistor including a third N-type drain region connected to the drain region, the gate oxide film, and a third gate electrode also serving as a word line; a fourth N-type MOS transistor A first transfer N comprising a source region, a fourth N-type drain region connected to the second N-type drain region, the gate oxide film, and a fourth gate electrode serving also as a word line; Channel MO
Forming an S-transistor, forming a first interlayer insulating film on the entire surface, and forming a first interlayer insulating film on the first interlayer insulating film;
Forming first and second ground contact holes reaching the N-type source region, and connecting to the first and second N-type source regions via the first and second ground contact holes. Forming a ground line to be formed, forming a second interlayer insulating film on the entire surface, forming an N-type polycrystalline silicon film on the entire surface, and patterning the polycrystalline silicon film to form a first
Forming a second polycrystalline silicon film pattern, forming a gate insulating film on the entire surface, and forming a first
Forming a conductive film, forming a fifth and a sixth gate electrode by patterning the first conductive film, and forming a P-type conductive film using the fifth and the sixth gate electrode as a mask.
A first P-type source region, a first channel region, a first P-type source region,
Forming a first P-type drain region, a second P-type source region, a second channel region, and a second P-type drain region in the second polycrystalline silicon film pattern; A fifth gate electrode, the gate insulating film, and the first gate electrode;
A first P-channel thin film transistor for load including a P-type source region, the first channel region, and the first drain region; a sixth gate electrode; the gate insulating film; Forming a second load P-channel thin film transistor including a second P-type source region, the second channel region, and the second drain region; and forming a third interlayer insulating film on the entire surface. Forming the third interlayer insulating film, the sixth gate electrode, the gate insulating film, the first P-type drain region, the second and first interlayer insulating films, and the gate oxide film; Forming a first node contact hole that penetrates and reaches the second gate electrode or the first N-type drain region; and forming the third interlayer insulating film, the fifth gate electrode, Gate insulating film, front A second node that penetrates a second P-type drain region, the second and first interlayer insulating films, and the gate oxide film and reaches the first gate electrode or the second N-type drain region; Forming a contact hole, forming a second conductive film on the entire surface, etching the entire surface, and leaving the second conductive film only inside the first and second node contact holes; Forming the first and second buried electrodes, forming a fourth interlayer insulating film on the entire surface, forming the fourth and third interlayer insulating films, the gate insulating film, 2. forming first and second bit contact holes penetrating the first interlayer insulating film and the gate oxide film and reaching the third and fourth N-type source regions; Via the first and second bit contact holes, Respectively the third
And a step of forming first and second bit lines connected to the fourth N-type source region.

The method of manufacturing a semiconductor memory device according to the present invention is characterized in that the second conductive film is made of a high melting point metal or a high melting point metal alloy film.

Further, in the semiconductor memory device according to the present invention, the first and second P-type source regions, and the first and second P-type source regions may be provided.
The step of forming the drain region of the mold also has a feature that it includes a step of forming a low-concentration P-type region at least between the drain region and the channel region.

[0042]

Next, the present invention will be described with reference to the drawings. FIGS. 1A and 1B show the first embodiment of the present invention.
FIG. 1C is a plan view of the SRAM memory cell portion showing the embodiment of FIG. 1, and FIG. 1C is a sectional view taken along the line AB.

Here, the driving N-channel MOS described above is used.
The steps up to the formation of the transistor, the transfer N-channel MOS transistor, and the ground line are the same as those in the prior art, and therefore will be briefly described.

As shown in FIGS. 1A and 1C, an element isolation oxide film 2 and a gate oxide film are respectively formed in an element isolation region and an element formation region on a surface of a P-type silicon substrate 1. 3 are provided. Drive gate electrodes 4a and 4b and transfer gate electrodes 5a and 5b are provided on the surface of the silicon substrate 1 with the gate oxide film 3 interposed therebetween. The N-type diffusion layers 6a, 6b, 6c, 6'a,
6'b and 6'c are formed.

The driving gate electrode 4a, the gate oxide film 3, the N-type diffusion layer 6a and the N-type diffusion layer 6b form the first
Of the driving N-channel MOS transistor TD1. Further, the driving gate electrode 4b, the gate oxide film 3, the N-type diffusion layer 6'a, and the N-type diffusion layer 6'b form the second
Of the driving N-channel MOS transistor TD2. Further, the transfer gate electrode 5a, the N-type diffusion layer 6
The first transfer MOS transistor TT1 is composed of b and the N-type diffusion layer 6c. The second transfer MOS transistor TT is formed by the transfer gate electrode 5b, the gate oxide film, the N-type diffusion layer 6'b, and the N-type diffusion layer 6'c.
2 are configured. Here, the transfer gate electrodes 5a, 5b also serving as the word lines WL are connected outside the memory cells.

These four N-channel MOS transistors are covered with a first interlayer insulating film 7 having a flat surface. As shown in FIG. 1A, the first interlayer insulating film 7 is provided with ground contact holes 8a and 8b reaching the N-type diffusion layers 6a and 6'a, respectively. The N-type diffusion layers 6a and 6'a are connected to the ground line 9 shown in FIG. 1C through the ground contact holes 8a and 8b. The surface of the first interlayer insulating film 7 including the ground line 9 is covered with a second interlayer insulating film 10 having a flat surface.

As shown in FIGS. 1B and 1C, on the surface of the second interlayer insulating film 10, a first and second polycrystalline silicon films made of a first polycrystalline silicon film are formed. A pattern is provided. The first polycrystalline silicon film pattern includes a high-concentration P-type polycrystalline silicon region 11a serving as a source region of one of the load P-channel TFTs, an N-type polycrystalline silicon region 12a serving as an N-type channel region of the TFT, and T
It is composed of a high-concentration P-type polycrystalline silicon region 13a serving as an FT drain region. Then, as shown in FIG.
The second polysilicon film pattern includes a high-concentration P-type polysilicon region 11b serving as a source region of the other load P-channel TFT, an N-type polysilicon region 12b serving as a TFT channel region, and a drain region of the TFT. And a high-concentration P-type polycrystalline silicon region 13b.

Here, the high-concentration P-type polycrystalline silicon region 1
1a and 11b each form a part of a power supply wiring, and both are connected outside the memory cell.

As shown in FIG. 1C, the first and second
On the surface of the polycrystalline silicon film pattern and the surface of the second interlayer insulating film 10, a TFT gate insulating film 14 is formed, and on the TFT gate insulating film 14, a second polycrystalline silicon film is formed. Gate electrode 15 for TFT
a and 15b are formed.

Thus, the TFT gate electrode 15
a, the TFT gate insulating film 14, and the high-concentration P-type polycrystalline silicon regions 11a and 13a.
The channel TFT TL1 is formed, and the TFT gate electrode 15b, the TFT gate insulating film 14, and the high concentration P are formed.
The other polycrystalline silicon regions 11b and 13b form another load P-channel TFT TT2.

Then, as shown in FIG.
The third interlayer insulating film 16 having a flat surface is deposited on the surfaces of the gate electrodes 15a and 15b for TFT and the surface of the gated insulating film 14 for TFT.

Then, as shown in FIG. 1C, a third interlayer insulating film 16, a TFT gate electrode 15b, a TFT gate insulating film 14, a high-concentration P-type polysilicon region 13 are formed.
a, a first node contact hole 17a penetrating through the second interlayer insulating film 10, the first interlayer insulating film 7, and the gate oxide film 3 and reaching both on the driving gate electrode 4b and the N-type diffusion layer 6b. Is provided. In addition, in the same manner, FIG.
As shown in (b), the third interlayer insulating film 16, the TFT gate electrode 15a, the TFT gate insulating film 14, the high-concentration P
Penetrating through the polycrystalline silicon region 13b, the second interlayer insulating film 10, the first interlayer insulating film 7, and the gate oxide film 3 to reach both on the driving gate electrode 4a and on the N-type diffusion layer 6'b. Two node contact holes 17b are provided.

As shown in FIG. 1C, buried electrodes 18a or 18b (not shown) are formed inside the node contact holes 17a and 17b. The N-type diffusion layer 6 is formed by the embedded electrode 18a.
b, the driving gate electrode 4b, the high-concentration P-type polycrystalline silicon region 13a, and the TFT gate electrode 15b are connected to form a connection point N1. Similarly, the N-type diffusion layer 6 ′ is formed by another embedded electrode 18 b (not shown).
b, the driving gate electrode 4a, the high-concentration P-type polycrystalline silicon region 13b, and the TFT gate electrode 15a are connected to form a connection point N2.

Here, in the vicinity of the node contact hole 17a, the TFT gate electrode 15b is arranged so as to overlap the node contact hole 17a and not protrude to the side of the TFT gate electrode 15a. node·
In the vicinity of the contact hole 17b, the TFT gate electrode 15
a is overlapped with the node contact hole 17b and the TFT
An important feature of the present invention is that it is arranged so as not to protrude to the side of the gate electrode 15b for use.

As shown in FIG. 1C, a fourth interlayer insulating film 19 is deposited on the surfaces of the buried electrodes 18a and 18b and the surface of the third interlayer insulating film 16. Further, the fourth interlayer insulating film 19 and the third interlayer insulating film 1
6. TFT gate insulating film 141, second interlayer insulating film 1
0, penetrating through the first interlayer insulating film 7 and the gate oxide film 3,
Bit line contact hole 20a reaching the N-type diffusion layer 6c
And 20b are open, and bit line 21a (BL
1) and the bit line 21b (BL2) are connected to the N-type diffusion layers 6c and 6'c through these contact holes, respectively.

Next, a manufacturing method according to the first embodiment of the present invention will be described with reference to FIGS. 2 and 3 are sectional views in the order of the manufacturing process of the SRAM memory cell.
One set of a pair of inverters and a pair of transfer N-channel MOS transistors is shown. Hereinafter, this one set will be described, but it is to be noted in advance that the method of forming the other sets is the same.

As shown in FIG. 2A, first, an element isolation oxide film 2 having a thickness of about 400 nm is formed in the element isolation region on the surface of the P-type silicon substrate 1 by a selective oxidation method or the like.
A gate oxide film 3 having a thickness of about 10 nm is formed in the element formation region by thermal oxidation or the like. Next, an N-type polycrystalline silicon film having a thickness of about 100 nm is formed on the entire surface by, for example, a low pressure chemical vapor deposition (LPCVD) method and an ion implantation method.
A tungsten silicide film of about 0 nm is formed on the entire surface. This laminated film is patterned by anisotropic reactive ion etching (RIE) to form a driving gate electrode 4b and a transfer gate electrode 5a having a polycide structure.

Element isolation oxide film 2 and drive gate electrode 4
b, the surface of the P-type silicon substrate 1 is formed by ion implantation of arsenic using the transfer gate electrode 5a as a mask.
An N-type diffusion layer 6b having a concentration of about ²⁰ to 10 ²¹ cm ^-3 ,
6c is formed.

Next, a first interlayer insulating film 7 having a flat surface and at least a bottom surface made of an oxide film is formed on the entire surface by, for example, an LPCVD method or a chemical mechanical polishing (CMP) method. The first interlayer insulating film 7 is formed, for example, as follows. A silicon oxide film having a thickness of about 100 nm is formed on the entire surface by LPCVD or the like.
A BPSG film (a silicon oxide film containing boron glass and phosphorus glass) having a thickness of about 600 nm is formed by a method or the like. Subsequently, after a heat treatment at 800 to 850 ° C. is performed, the surface is flattened by CMP.

A ground contact hole (not shown) reaching the N-type diffusion layer by RIE is formed in the first interlayer insulating film 7. Then, an N-type polycrystalline silicon film having a thickness of about 100 nm is formed on the entire surface by LPCVD, ion implantation, or the like.
Further, a tungsten silicide film having a thickness of about 100 nm is formed on the entire surface by LPCVD or the like, and a ground line 9 having a polycide structure is formed by RIE.

Subsequently, a second interlayer insulating film 10 having a flat surface and at least an upper layer made of a silicon oxide film is formed on the entire surface by LPCVD, CMP, or the like. This second interlayer insulating film 10 is also formed in the same manner as the first interlayer insulating film.

An amorphous silicon film having a thickness of about 40 nm is formed on the entire surface of the second interlayer insulating film 10 by LP.
It is formed by a CVD method or the like. Heat treatment is performed at a temperature of about 600 ° C. for about 10 hours, and this amorphous silicon film changes into a polycrystalline silicon film. Further, an N-type impurity is introduced by an ion implantation method or the like to form an N-type polycrystalline silicon film of about 10 ¹⁶ to 10 ¹⁸ cm ⁻³ (the above-described first polycrystalline silicon film).

This first polycrystalline silicon film is patterned by RIE to form a first polycrystalline silicon film pattern 11'a and a second polycrystalline silicon film pattern 11'b. Then, a TFT gate insulating film 14 having a thickness of about 15 nm is formed on the entire surface by LPCVD or the like, and further has a concentration of about 10 ¹⁶ to 10 ¹⁹ cm ^{-3 on the} entire surface by LPCVD, ion implantation, or the like. An N-type or P-type second polycrystalline silicon film (described above) is formed. This second polycrystalline silicon film is patterned by RIE, and TFT gate electrodes 15a and 15b are formed.
Is formed (FIG. 2A).

Next, the TFT gate electrodes 15a and 1
Using Pb 5b as a mask, P-type impurity ions are implanted into the entire surface, and a high-concentration P-type polysilicon region 11 is self-aligned.
a, 11b and 13a are formed. In the first polycrystalline silicon film pattern 11'a, the TFT gate electrode 1
The portions covered with 5a and 15b respectively have TF
N-type polycrystalline silicon region 12a serving as a T channel region
In addition, a region 13'a where no impurity is implanted is left (FIG. 2B).

The second polycrystalline silicon film pattern 1
Although not shown in FIG. 1'b, the same occurs.

Subsequently, for example, the LPCVD method and the CMP
Thus, the third interlayer insulating film 16 is formed on the entire surface. This third interlayer insulating film 16 is also formed in the same manner as the second interlayer insulating film 10 (FIG. 2C).

Next, the third interlayer insulating film 1 is formed by RIE.
6, TFT gate electrode 15b, TFT gate insulating film 14, high-concentration P-type polycrystalline silicon region 13a, region 13'a without impurity implantation, second interlayer insulating film 10, first interlayer insulating film 7, gate oxide film 3 to reach both on the drive gate electrode 4b and the N-type diffusion layer 6b.
The contact hole 17a is opened. At this time, the node
In the vicinity of the contact hole 17a, the TFT gate electrode 15b is arranged so as to overlap with the node contact hole 17a and not to protrude from the node contact hole 17a on the side in the direction of the TFT gate electrode 15a.

The node contact hole 17a is formed, for example, as follows. First, the third interlayer insulating film 16 is etched by RIE using CHF ₃ or the like as an etching gas. Next, the TFT gate electrode 15b is etched by RIE using an etching gas composed of, for example, HBr and Cl ₂ , and the TFT gate insulating film 14 is etched by RIE using, for example, CHF ₃ as an etching gas. You. Subsequently, a high-concentration P-type polycrystalline silicon region 1 is formed by RIE using an etching gas composed of, for example, HBr and Cl _2.
3a, the region 13'a without impurity implantation is etched, and finally, the second interlayer insulating film 10, the first interlayer insulating film 7, and the gate oxide film 3 are successively formed by RIE using, for example, CHF ₃ as an etching gas. Etched.

Here, the node contact hole 17a is
N-type impurity ions such as phosphorus or arsenic ions are implanted through the node contact hole 17a in order to prevent the leak current of the diffusion layer from increasing when overlapping the edge of the element isolation oxide film 2 due to misalignment. (FIG. 2 (d)).

Next, as shown in FIG. 3, a buried electrode 18a is formed inside the node contact hole 17a. The embedded electrode 18a is formed as follows, for example.

[0071] First, LPCVD method, an ion implantation method or the like, N-type polycrystalline silicon film having an impurity concentration of the entire surface 10 ¹⁹ ~10 ²¹ cm ^-3 is formed. The thickness of this polycrystalline silicon film is desirably about the same as the diameter of the node / contact hole. Next, the polycrystalline silicon film is entirely etched by isotropic dry etching to form a buried electrode 18a made of polycrystalline silicon only inside the node contact 17a.

The embedded electrode 18a is formed as follows. First, in order to prevent a reaction between tungsten and silicon, a titanium film having a thickness of about 50 nm and a thickness of 100 nm
About titanium nitride films are sequentially formed. Next, LP on the whole surface
A tungsten film is grown by a CVD method or the like. The film thickness is desirably about the same as the contact hole diameter. Then, by the isotropic etching, the tungsten film, the titanium nitride film,
The titanium film is sequentially etched entirely, and buried electrodes 18a made of these refractory metals are formed only inside the node contacts 17a (FIG. 3A).

Subsequently, a film thickness of 10
A fourth interlayer insulating film 19 of about 0 nm is formed on the entire surface.
The fourth interlayer insulating film 19 may be made of silicon oxide or BPSG.
If the buried electrode 18a is made of a metal having a high melting point such as tungsten, it may be formed by a normal pressure CVD method having an upper limit of about 500 ° C., a plasma CVD method, or the like.

Next, the fourth interlayer insulating film 19 is formed by RIE.
The third interlayer insulating film 16, the TFT gate insulating film 14, the second
A bit line contact hole 20a penetrating through the interlayer insulating film 10, the first interlayer insulating film 7, and the gate oxide film 3 and reaching the N-type diffusion layer 6c is opened (FIG. 3B).

Further, a titanium film having a thickness of about 50 nm and a titanium nitride film having a thickness of about 100 nm are sequentially formed on the entire surface by sputtering or the like, and a tungsten film is grown on the entire surface by LPCVD or the like. The thickness is desirably about the same as the contact hole diameter. Then, the tungsten film, the titanium nitride film, and the titanium film are sequentially and entirely etched by isotropic etching, and a buried electrode (not shown) made of tungsten is formed only inside the bit contact 20a.
Is formed, and a titanium film, a titanium nitride film, and an aluminum film are sequentially formed on the entire surface. These aluminum film, titanium nitride film, and titanium film are sequentially patterned, and FIG.
The bit line 21a shown in (c) is formed, and one set of the memory cell of the present invention is formed.

According to the structure and the manufacturing method of the present invention, the high-concentration P-type polysilicon region 13a or 13b serving as the P-type drain region of the load P-channel TFT.
And the region without impurity implantation between the buried electrode 18a and 18b. Therefore, even if the heat treatment is performed at a low temperature and for a short time in the upper gate type TFT, the problem that the current supply capability of the TFT is extremely reduced due to the parasitic resistance does not occur.

After the opening of the node / contact hole 17a or 17b and the peeling of the photoresist, the TFT gate insulating film 14 is not exposed on the surface. Even if the natural oxide film is removed with diluted hydrofluoric acid, local thinning or contamination of the TFT gate insulating film does not occur.
Then, the gate withstand voltage of the TFT does not extremely deteriorate.

Further, the embedded electrode 18a or 18
If b is formed of a high melting point metal such as tungsten, a parasitic PN diode will not be formed at the node / contact hole portion, and a reduction in the current supply capability of the TFT can be prevented.

Next, a second embodiment of the present invention will be described with reference to FIG. The first embodiment is an example having a TFT having a single drain structure as a load element.
In the second embodiment, an offset is provided in the drain portion,
LDO (Light) in which a low-concentration P-type region is provided in that portion.
This is an example in which a TFT having a (ly Doped Offset) structure is provided as a load element. FIG. 4A shows the SRA
FIG. 4B is a plan view of the M memory cell, and FIG.
It is sectional drawing cut | disconnected by CD shown to (a).

Here, except for the load P-channel TFT portion of the SRAM memory cell, it is the same as that described in the first embodiment, and therefore the description will be simplified below.

As shown in FIG. 4B, the driving N-channel MOS transistor and the transfer N-channel MOS transistor constituting the SRAM memory cell have flat surfaces as described in the first embodiment. It is covered by the second interlayer insulating film 10.

As shown in FIGS. 4A and 4B, on the surface of the second interlayer insulating film 10, first and second polycrystalline silicon films made of a first polycrystalline silicon film are provided. A silicon film pattern is provided. The first polycrystalline silicon film pattern includes a high-concentration P-type polycrystalline silicon region 11a serving as a source region of one load P-channel TFT and an N-type polycrystalline silicon region 12 serving as an N-type channel region of the TFT.
a, low-concentration P-type polycrystalline silicon region 22a, high-concentration P-type polycrystalline silicon region 13a serving as a drain region of a TFT
Consists of The second polycrystalline silicon film pattern includes a high-concentration P-type polycrystalline silicon region 11b serving as a source region of the other load P-channel TFT, an N-type polycrystalline silicon region 12b serving as a TFT channel region, and a low-concentration polycrystalline silicon region 12b. P
And a high-concentration P-type polycrystalline silicon region 13b serving as a drain region of the TFT.

Here, high-concentration P-type polycrystalline silicon region 1
1a and 11b each form a part of a power supply wiring, and both are connected outside the memory cell.

As shown in FIG. 4B, the first and second
On the surface of the polycrystalline silicon film pattern and the surface of the second interlayer insulating film 10, a TFT gate insulating film 14 is formed, and on the TFT gate insulating film 14, a second polycrystalline silicon film is formed. Gate electrode 15 for TFT
a and 15b are formed.

As described above, the TFT gate electrode 15
a, a TFT gate insulating film 14, high-concentration P-type polycrystalline silicon regions 11a and 13a, and a low-concentration P-type polycrystalline silicon region 22a.
TL1 is formed, and the TFT gate electrode 15 is formed.
b, the gate insulating film for TFT 14, the high-concentration P-type polycrystalline silicon regions 11b and 13b, and the low-concentration P-type polycrystalline silicon region 22b.
TT2 is configured.

Then, as shown in FIG.
The third interlayer insulating film 16 having a flat surface is deposited on the surfaces of the gate electrodes 15a and 15b for TFT and the surface of the gated oxide film 14 for TFT.

Then, the third interlayer insulating film 16, the TFT gate electrode 15b, the TFT gate insulating film 14, the high-concentration P
-Type polycrystalline silicon region 13a, region 1 without impurity implantation
3'a, the second interlayer insulating film 10, the first interlayer insulating film 7, and the gate oxide film 3, and the N
A first node contact hole 17a is provided which reaches both sides of the type diffusion layer 6b. Similarly, as shown in FIG. 4A, the second node contact hole 1
7b is provided.

As shown in FIG. 4B, buried electrodes 18a and 18b (not shown) are formed inside these node contact holes 17a and 17b. The N-type diffusion layer 6 is formed by the embedded electrode 18a.
b, the driving gate electrode 4b, the high-concentration P-type polycrystalline silicon region 13a, and the TFT gate electrode 15b are connected to form a connection point N1. Similarly, the N-type diffusion layer 6 ′ is formed by another embedded electrode 18 b (not shown).
b, the driving gate electrode 4a, the high-concentration P-type polycrystalline silicon region 13b, and the TFT gate electrode 15a are connected to form a connection point N2.

As shown in FIG. 4B, a fourth interlayer insulating film 19 is deposited on the surface of the buried electrode 18a or 18b and the surface of the third interlayer insulating film 16.

Thereafter, as in the first embodiment, a bit line contact hole is opened, and a bit line is formed.

As a manufacturing method of forming the drain region of such a load P-channel TFT into an LDO structure, there is a method of selectively ion-implanting boron impurities using a resist pattern formed by a usual photolithography technique. Be taken.

According to such a structure and a manufacturing method, it is possible to realize an SRAM memory cell having a TFT having an LDO structure as a load element capable of alleviating a drain electric field and securing a current driving capability as compared with a single drain structure. At this time, the high-concentration P-type polysilicon regions 13a and 13b and the low-concentration P-type polysilicon regions 22a and 22b are
Since it is formed in a self-aligned manner with respect to the gate electrode for use, the controllability of the channel length is good, and the problem that the current supply capability of the TFT is extremely reduced due to the parasitic resistance at the node / contact hole portion does not occur. Further, the gate insulation withstand voltage does not extremely deteriorate.

Next, a third embodiment of the present invention will be described with reference to FIG. This is a case where the source / drain region of the load P-channel TFT has an LDD structure in which the source / drain region is formed in a self-aligned manner with respect to the TFT gate electrode.
Here, FIG. 5A is a plan view of the SRAM memory cell. FIG. 5B is a cross-sectional view taken along the line EF shown in FIG.

In this case as well, except for the load P-channel TFT portion of the SRAM memory cell, which is the same as that described in the first embodiment, the description is simplified below.

As shown in FIG. 5B, the driving N-channel MOS transistor and the transfer N-channel MOS transistor constituting the SRAM memory cell are covered with a second interlayer insulating film 10 having a flat surface. . Then, as shown in FIGS. 5A and 5B, on the surface of the second interlayer insulating film 10, a first and second polycrystalline silicon film patterns made of the first polycrystalline silicon film are formed. Is provided. The first polycrystalline silicon film pattern includes a high-concentration P-type polycrystalline silicon region 11a, a low-concentration P-type polycrystalline silicon region 23a, which is a source region of one load P-channel TFT, and a TFT N-type channel region. It comprises a certain N-type polycrystalline silicon region 12a, a low-concentration P-type polycrystalline silicon region 24a, and a high-concentration P-type polycrystalline silicon region 13a serving as a drain region of a TFT. Then, as shown in FIG. 5A, the second polycrystalline silicon film pattern has a high-concentration P film serving as a source region of the other load P-channel TFT.
-Type polycrystalline silicon region 11b, low-concentration P-type polycrystalline silicon region 23b, TFT channel region N-type polycrystalline silicon region 12b, low-concentration P-type polycrystalline silicon region 2
4b, a high-concentration P-type polycrystalline silicon region 13b which becomes the drain region of the TFT.

Here, the high-concentration P-type polycrystalline silicon region 1
1a and 11b each form a part of a power supply wiring, and both are connected outside the memory cell.

As shown in FIG. 5B, the first and second
On the surface of the polycrystalline silicon film pattern and the surface of the second interlayer insulating film 10, a TFT gate insulating film 14 is formed, and on the TFT gate insulating film 14, a second polycrystalline silicon film is formed. Gate electrode 15 for TFT
a and 15b are formed. And these T
Sidewall insulating films 25a and 25b are formed on the side walls of FT gate electrodes 15a and 15b, respectively.

Thus, the TFT gate electrode 15
a, a TFT gate insulating film 14, high-concentration P-type polycrystalline silicon regions 11a and 13a, and low-concentration P-type polycrystalline silicon regions 23a and 24a, to constitute one load P-channel TFT TL1, The other load P-channel TFT TT2 is composed of the TFT gate electrode 15b, the TFT gate insulating film 14, the high-concentration P-type polycrystalline silicon regions 11b and 13b, and the low-concentration P-type polycrystalline silicon regions 23b and 24b. ing. Then, as shown in FIG. 5B, the TFT gate electrode 15 is formed.
On the surfaces of a and 15b, a third interlayer insulating film 16 having a flat surface is deposited.

Then, the third interlayer insulating film 16, the TFT gate electrode 15b, the sidewall insulating film 25b, the high-concentration P-type polysilicon region 13a, the second interlayer insulating film 10,
A first node contact hole 17a is provided which penetrates the first interlayer insulating film 7 and the gate oxide film 3 and reaches both on the driving gate electrode 4b and on the N-type diffusion layer 6b. Similarly, as shown in FIG.
The node contact hole 17b is provided.

As shown in FIG. 5B, buried electrodes 18a or 18b (not shown) are formed inside these node / contact holes 17a. The buried electrode 18a connects the N-type diffusion layer 6b, the driving gate electrode 4b, the high-concentration P-type polycrystalline silicon region 13a, and the TFT gate electrode 15b to form a connection point N1.
Is configured. Similarly, other embedded electrodes 18b
(Not shown), the N-type diffusion layer 6′b, the driving gate electrode 4a, the high-concentration P-type polycrystalline silicon region 13b, and the TFT gate electrode 15a are connected to each other to form a connection point N2.
Is configured. Then, as shown in FIG.
On the surface of the buried electrode 18a or 18b and the surface of the third interlayer insulating film 16, a fourth interlayer insulating film 19 is deposited.

Thereafter, bit line contact holes 20a and 20b are opened in the same manner as in the first and second embodiments. Then, a bit line is formed.

As a manufacturing method of forming the source / drain regions of such a load P-channel TFT into the LDD structure, boron as a P-type impurity is formed by using a sidewall insulating film formed on the side wall of the gate electrode for the TFT as a mask. A method of implanting ions into the entire surface is used. Here, the sidewall insulating film is usually formed by an anisotropic RIE with an entire surface film of a silicon oxide film.

According to such a structure and a manufacturing method, it is possible to realize an SRAM memory cell having a TFT having a LDD structure as a load element capable of relaxing a drain electric field and securing a current driving capability as compared with a single drain structure. At this time, since both the high-concentration P-type polycrystalline silicon region and the low-concentration P-type polycrystalline silicon region are formed in a self-alignment manner with respect to the TFT gate electrode, the controllability of the channel length and the length of the LDD region is good. The problem that the current supply capability of the TFT is extremely reduced due to the parasitic resistance in the node contact hole portion does not occur. Further, the gate insulation withstand voltage does not extremely deteriorate.

In the third embodiment, since the sidewall insulating films 25a and 25b are formed, a region without impurity implantation is easily formed by the conventional method, and the parasitic resistance is further increased. For this reason, it is difficult to form such an LDD structure with the conventional technology. However, in the present invention, such a problem can be easily solved and the formation of the LDD structure can be simplified.

[0105]

As described above, according to the semiconductor memory device of the present invention, four N-channel transistors M formed on the substrate surface are provided.
A node at which a pair of CMOS inverters are cross-connected in an SRAM memory cell including an OS transistor and a pair of upper gate P-channel TFTs formed on a surface of an interlayer insulating film covering the N-channel MOS transistor. A node / contact hole is provided on the interlayer insulating film covering the P-channel TFT, the gate electrode of the P-channel TFT, the gate insulating film of the P-channel TFT, the P-type drain region of the P-channel TFT, and the substrate surface at the contact portion. Through the interlayer insulating film covering the two N-channel MOS transistors, the gate oxide film of the N-channel MOS transistor, to the gate electrode of the N-channel MOS transistor or the N-type drain region; With the embedded electrode provided inside the hole In the vicinity of the node contact hole, the gate electrode of one P-channel TFT overlaps the node contact hole and has a structure in which the gate electrode is arranged so as not to protrude toward the gate electrode of the other TFT. .

Therefore, in the step of forming the P-type source / drain region or the P-type LDD region of the P-channel TFT in a self-alignment manner, the P-type TFT is formed between the P-type drain region and the buried electrode. In addition, a region without impurity implantation is not left, and even if the heat treatment is performed at a low temperature and for a short time, the problem that the current supply capability of the TFT is extremely reduced due to the parasitic resistance can be avoided. For example, if a parasitic resistance occurs in the conventional technology, the resistance is 10 ¹⁰ Ω in sheet resistance.
/ □, and the current supply capability of the load element is limited not by the on-state current of the TFT but by this parasitic resistance, which is as low as about 10 ⁻¹⁰ to 10 ⁻⁹ A. However, if the parasitic resistance is eliminated according to the present invention, the original ON current of the TFT becomes the current supply capability of the load element, and a current of 10 ⁻⁷ A or more can be supplied.

Further, since the gate insulating film of the TFT is not exposed on the surface after the opening of the node / contact hole and the peeling of the photoresist, the natural oxide film formed by the peeling of the photoresist by oxygen plasma, a cleaning process, or the like is removed. Even if it is removed with diluted hydrofluoric acid, local thinning of the gate insulating film, contamination, and the like do not occur, and it is possible to prevent the gate insulating withstand voltage from being extremely deteriorated.

Further, if the buried electrode is formed of a refractory metal such as tungsten, a parasitic PN diode is not formed at the node / contact hole, and the current supply capability of the TFT may be reduced. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view of a memory cell illustrating a first embodiment of the present invention.

FIG. 2 is a sectional view of the memory cell according to the first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a sectional view of the memory cell according to the first embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a plan view and a cross-sectional view of a memory cell illustrating a second embodiment of the present invention.

FIG. 5 is a plan view and a cross-sectional view of a memory cell illustrating a third embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of an SRAM memory cell.

FIG. 7 is a cross-sectional view of a memory cell for explaining a conventional technique.

FIG. 8 is a cross-sectional view of a memory cell in the order of manufacturing steps for explaining a conventional technique.

[Explanation of symbols]

1, 101 silicon substrate 2, 102 element isolation oxide film 3, 103 gate oxide film 4a, 4b, 104 drive gate electrode 5a, 5b, 105 transfer gate electrode 6a, 6b, 6c, 6'a, 6'b, 6'c N-type diffusion layer 7, 107 First interlayer insulating film 8a, 8b Ground contact hole 9, 108 Ground line 10, 109 Second interlayer insulating film 11a, 11b, 13a, 13b High-concentration P-type polycrystalline silicon region 11 'a First polysilicon film pattern 11'b Second polysilicon film pattern 12a, 12b, 117 N-type polysilicon region 13'a, 13'b, 116', 118 'Region without impurity implantation 14, 120 TFT gate insulating film 15a, 15b, 122a, 122b TFT gate electrode 16, 124 Third interlayer insulating film 17a, 17b Node contact Hole 18a, 18b, 112, 113 buried electrode 19 fourth interlayer insulating film 20a, 20b, 111 bit line contact hole 21a, 21b, 125 bit line 22a, 22b low-concentration P-type polycrystalline silicon region 23a, 23b, 24a, 24b Low-concentration P-type polycrystalline silicon region 25a, 25b Side wall insulating film 106a, 106b N-type diffusion layer 110 Connection contact hole 114, 115 Titanium silicide layer 116, 118 High-concentration P-type polycrystalline silicon region 121 Power supply line 123 Protection Insulating film TD1, TD2 Transfer N-channel MOS transistor TT1, TT2 Transfer N-channel MOS transistor TL1, TL2 Load P-channel MOS transistor N1, N2 Connection point WL Word line BL1, BL2 Bit line

Claims (6)

[Claims] 1. A static memory cell formed by a pair of information transfer MOSFETs formed on the surface of a semiconductor substrate, a pair of drive MOSFETs forming a flip-flop circuit, and a pair of load thin film transistors. A first N-type source region connected to a ground line;
A first driving N formed on a surface of a silicon substrate, comprising a drain region of a type, a gate oxide film, and a first gate electrode.
A channel MOS transistor, a second N-type source region connected to a ground line, a second N-type drain region, the gate oxide film, and a second gate electrode, provided on the surface of the silicon substrate. Second drive N-channel MO
An S transistor, a third N-type source region connected to one of the pair of bit lines, a third N-type drain region connected to the first N-type drain region, the gate oxide film, A first transfer N-channel MOS transistor provided on the surface of the silicon substrate, and a fourth N-type MOS transistor connected to the other of the pair of bit lines. And a fourth N-type drain region connected to the second N-type drain region, the gate oxide film, and a fourth gate electrode connected to the word line. A second transfer N-channel MOS transistor provided on a surface thereof, wherein the first and second drive N-channel MOS transistors and the first and second transfer N-channel MOS transistors are provided. Has a first interlayer insulating film covering the surface of data, the composed of polycrystalline silicon film provided on the second interlayer insulating film surface that covers the ground line, first connected to a power supply line 1
A first polycrystalline silicon film pattern comprising a P-type source region, a first channel region and a first P-type drain region; and a first polycrystalline silicon film pattern comprising the polycrystalline silicon film and connected to the power supply line. A second polycrystalline silicon film pattern including a second P-type source region, a second channel region, and a second P-type drain region; and a surface covering the first and second polycrystalline silicon film patterns. A gate insulating film provided on a surface of the second interlayer insulating film; and a portion that covers the first channel region via the gate insulating film and extends over the second P-type drain region. A fifth gate electrode formed on the surface of the gate insulating film, and covering the second channel region via the gate insulating film, and extending over the first P-type drain region. Having a portion to A sixth gate electrode formed on the surface of a gate insulating film, the fifth gate electrode, the gate insulating film, the first P-type source region, the first channel region, and A first load P-channel thin film transistor including a first P-type drain region, the sixth gate electrode, the gate insulating film, the second P-type source region, the second channel region, A second interlayer insulating film covering the first and second load P-channel thin-film transistors, the second interlayer insulating film including a second load P-channel thin-film transistor including the second P-type drain region; An interlayer insulating film, the sixth gate electrode, the gate insulating film, the first P-type drain region, the second
A first node contact hole penetrating through the interlayer insulating film, the first interlayer insulating film, and the gate oxide film to reach the second gate electrode or the first N-type drain region; The third interlayer insulating film, the fifth gate electrode, the gate insulating film, the second P-type drain region, the second interlayer insulating film, the first interlayer insulating film, the gate oxide film And a second node contact hole reaching the first gate electrode or the second N-type drain region, and a conductive layer formed inside the first node contact hole. A first buried electrode formed inside the second node contact hole;
A conductive second buried electrode, wherein the first buried electrode allows the second gate electrode or the first N-type drain region, the first P-type drain region, the sixth buried electrode, A gate electrode is connected to each other, and the first buried electrode connects the first gate electrode or the second N-type drain region, the second P-type drain region, and the fifth gate electrode to each other. Wherein the sixth gate electrode overlaps the first node contact hole in the vicinity of the first node contact hole, and has no protruding portion on the side of the fifth gate electrode. In the vicinity of the second node contact hole, the fifth gate electrode overlaps with the second node contact hole and protrudes toward the sixth gate electrode. A semiconductor memory device characterized by being arranged so as not to have a portion. 2. The semiconductor memory device according to claim 1, wherein said first and second buried electrodes are made of a high melting point metal film or an alloy film containing a high melting point metal. 3. The semiconductor memory device according to claim 1, wherein said first and second load P-channel thin-film transistors have a low-concentration P-type region at least between a drain region and a channel region. 4. An element isolation oxide film and a gate oxide film are respectively formed on an element isolation region and an element formation region on a surface of a silicon substrate, and then a first N-type source region and a first N-type source region are formed on the surface of the silicon substrate. A first driving N-channel MOS transistor including a first N-type drain region, the gate oxide film, and a first gate electrode; a second N-type source region; and a second N-type drain. A second driving N-channel MOS transistor including a region, the gate oxide film, and a second gate electrode, a third N-type source region, and a first N-type drain region connected to the first N-type drain region. No. 3 N-type drain region, the gate oxide film, and a third gate electrode for a transfer which is also a word line.
An S transistor, a fourth N-type source region, and a second N-type source region.
Forming a first transfer N-channel MOS transistor including a fourth N-type drain region connected to the negative-type drain region, the gate oxide film, and a fourth gate electrode also serving as a word line. Forming a first interlayer insulating film on the entire surface, and forming a first interlayer insulating film on the first interlayer insulating film to reach the first and second N-type source regions;
Forming a second ground contact hole;
Forming a ground line connected to the first and second N-type source regions through a second ground contact hole; forming a second interlayer insulating film on the entire surface; A step of forming a crystalline silicon film, a step of patterning the polycrystalline silicon film to form first and second polycrystalline silicon film patterns, a step of forming a gate insulating film over the entire surface, Forming a first conductive film; patterning the first conductive film to form fifth and sixth gate electrodes; using the fifth and sixth gate electrodes as a mask to form a P-type impurity. And introducing a first P-type source region, a first channel region, and a first P-type source region into the first polycrystalline silicon film pattern.
Forming a second P-type source region, a second channel region, and a second P-type drain region in the second polycrystalline silicon film pattern; Gate electrode, the gate insulating film, and the first P
A first P-channel thin-film transistor for load comprising a source region of the type, the first channel region, and the first drain region; the sixth gate electrode; the gate insulating film; Forming a second load P-channel thin-film transistor comprising the P-type source region, the second channel region, and the second drain region; and forming a third interlayer insulating film on the entire surface. The third interlayer insulating film, the sixth gate electrode, the gate insulating film, the first P-type drain region, the second and first interlayer insulating films, the gate oxide film, Forming a first node contact hole reaching the second gate electrode or the first N-type drain region; and forming the third interlayer insulating film, the fifth gate electrode, and the gate insulating film. ,
A second penetrating the second P-type drain region, the second and first interlayer insulating films, the gate oxide film and reaching the first gate electrode or the second N-type drain region. The step of forming the node contact hole, the second conductive film is formed on the entire surface, and the entire surface is etched.
Forming the first and second buried electrodes so that the second conductive film remains only inside the first and second node contact holes; and forming a fourth interlayer insulating film on the entire surface. And forming the fourth,
A third interlayer insulating film, the gate insulating film, the second and first
The first and second N-type source regions penetrating through the interlayer insulating film and the gate oxide film to reach the third and fourth N-type source regions.
Forming a first bit contact hole, and connecting the third and fourth N-type source regions via the first and second bit contact holes, respectively.
And a step of forming a second bit line. 5. The method according to claim 4, wherein the second conductive film is made of a high melting point metal or a high melting point metal alloy film.
The manufacturing method of the semiconductor memory device described in the above. 6. The step of forming the first and second P-type source regions and the first and second P-type drain regions comprises the step of forming a low-concentration P-type region between at least the drain region and the channel region. 5. The method according to claim 4, further comprising the step of forming a mold region.