JPS63293882A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize an element with large driving current output by providing a plurality of gate electrodes on a vertical-type MOS field effect transistor and constituting the electrodes so that vertical channel section is formed on its both sides. CONSTITUTION:A source region 2 is embedded in a P-type substrate 1 and a P-type epitaxial layer 4 and drain region 3 are formed on the surface. Two gate electrodes 6, 6 are formed within the epitaxial layer 4 and a gate oxidation film 5 is formed on its both sides. With such constitution, a vertical MOS field effect transistor is constructed. By applying voltage to the source region 2 and drain region 3 and increasing the potential of the gate electrode 6, a channel region 12 is formed vertical to the surface of the semiconductor chip near the gate electrode 6 on the P-type epitaxial layer 4. At this time, the channel region 12 is formed on both right and left sides of the gate electrode 6 so that it is possible to feed large driving current by providing a plurality of the gate electrodes 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to the structure of a MOS field effect transistor with high driving ability.

[Conventional technology]

Conventionally, MO8 field effect used in drive circuits of external devices,
Transistors are usually formed with a large channel width in order to obtain the necessary driving capability.

[Problem that the invention seeks to solve]

MOS field effect transistors with such high driving ability will naturally be used in the output circuits of MO8 type semiconductor integrated circuit devices, but the large channel width increases the area occupied by the substrate, so it is necessary to increase the semiconductor chip size. It has the disadvantage of making it worse. In particular, in MO3 type semiconductor integrated circuit devices developed for the purpose of high driving ability, the influence is extremely serious, as the chip size becomes quite large simply due to the structure of this output transistor. .

In view of the above situation, an object of the present invention is to
An object of the present invention is to provide a semiconductor device circuit device equipped with a high driving capacity MOS field effect transistor without increasing the size.

[Means for solving problems]

According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate of one conductivity type, a buried layer of an opposite conductivity type embedded in the semiconductor substrate, and semiconductor layers of one conductivity type and an opposite conductivity type sequentially stacked on the substrate. a vertical structure in which a polycrystalline silicon layer is formed as a source region, a channel region, and a drain region, respectively, and a polycrystalline silicon layer embedded vertically in the semiconductor layer of one conductivity type with a gate oxide film provided on both sides thereof as a gate electrode. MO of
8 field effect transistors.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) and 1(b) are a schematic plan view and a sectional view taken along line AA' of an MO3 type semiconductor integrated circuit device, respectively, showing an embodiment of the present invention. According to this embodiment, the semiconductor integrated circuit device of the present invention includes a P-type semiconductor substrate 1, an N+ buried layer buried in the P-type semiconductor substrate 1, and a P-type epitaxial layer 4 sandwiched between the substrate 1 and the P-type semiconductor substrate 1. -N deposited in
type polycrystalline silicon layers as a source region 2 and a drain region 3, respectively, and two polycrystalline silicon layers embedded in a P-type epitaxial layer 4 with gate oxide films 5 provided vertically on both sides respectively. Each of the MO3 field effect transistors has a vertical structure and has a gate electrode 6. Here, 7°8, 9, 10 and 11 are an element isolation insulating film, an N+ diffusion region for extracting a drain electrode, a source electrode, a train electrode, and a field insulating film, respectively, and 13 is a gate contact hole.

A semiconductor integrated circuit device having this structure can be easily manufactured by the following method. That is, first, a heavily doped N-type buried layer is formed on the surface of the P-type semiconductor substrate 1, and then the P-type epitaxial layer 4 is grown thereon. Next, the inside of this P-type epitaxial layer 4 is selectively etched away to form a gate buried portion, and a silicon oxide film is formed on the entire side and bottom surface, and then a polycrystalline silicon layer is formed on the entire surface. The polycrystalline silicon layer and silicon oxide film are selectively removed again to form gate oxide film 5 and gate electrode 6, respectively. Here, oxidation treatment is performed again to form polycrystalline silicon.
After removing the oxide film other than the upper surface of the gate 6, an N-type polycrystalline silicon layer is formed on the entire surface, and a field oxide Ill is formed on the surface. Thereafter, contact holes are opened to take potentials of the source, drain, and gate, respectively, and required electrode wiring is performed using known techniques.

The MO8 field effect transistor of this embodiment operates as follows. That is, when a voltage is applied to the source region 2 and the drain region 3 while keeping the potential of the gate electrode 6 at OV, no current flows between the source and drain composed of the N-type semiconductor layer due to the presence of the P-type epitaxial layer 4. Not flowing.

Then, when the potential of the gate electrode 6 is increased, electrons gather near the gate electrode 6 of the P-type epitaxial layer 4, and N
An inverted channel region 12 is now formed, and a source-drain current flows from the drain 2 through this conductive bus. That is, the operation of a normal MO5 field effect transistor occurs in a direction perpendicular to the surface of the semiconductor chip. At this time, since two channel regions 12 are formed on each of the left and right sides of one gate electrode 6, by providing a plurality of gate electrodes 6, a very large drive current can be output. In addition, since the gate length can be controlled by the thickness of the P-type epitaxial N4, it is independent of the mask alignment accuracy.
It is also possible to easily form high-speed devices with gate lengths shorter than conventional ones.

FIG. 2 is a plan view showing the main parts of another embodiment of the present invention. According to this embodiment, a plurality of gate electrodes 6 are provided.
The periphery of the upper surface is formed of a commonly connected plate-shaped polycrystalline silicon layer 14 except for the channel region 12. Here, 15
0 indicates a gate contact hole. According to this embodiment, the number of channel regions 12 can be significantly increased, so that a very large drive current can be output.

[Effects of the Invention] As explained in detail above, according to the present invention, it is possible to obtain a vertical MO8 field effect transistor element having a structure in which the channel current flows perpendicularly to the semiconductor substrate and having a large drive current output. , it is possible to easily realize an MO8 type semiconductor integrated circuit device having both high drive and high speed capabilities without increasing the chip size.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show an embodiment of the present invention.
A schematic plan view of an O3 type semiconductor integrated circuit device and its A
-A' sectional view and FIG. 2 are plan views showing main parts of another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Source region, 3...
・Drain region, 4... P-type epitaxial layer, 5.
... Gate oxide film, 6... Gate electrode, 7... Element isolation insulating film, 8... N+ diffusion region for drain electrode number, 9... Source electrode, 10... Drain electrode, 11
...Field insulating film, 12...Channel region, 1
3.15... Gate contact hole, 14... Plate-shaped polycrystalline silicon layer. /Mushi Agent Patent Attorney Susumu Uchihara〒゛-Toko no Taku No. 8b 1

Claims (1)

[Claims] A semiconductor substrate of one conductivity type, a buried layer of an opposite conductivity type embedded in the semiconductor substrate, and semiconductor layers of one conductivity type and opposite conductivity type sequentially stacked on the substrate are used as a source region, a channel region, and a drain region, respectively. , further comprising a vertically structured MOS field effect transistor having a polycrystalline silicon layer buried in the one conductivity type semiconductor layer with gate oxide films vertically provided on both sides thereof as a gate electrode. Semiconductor integrated circuit device.