JPS63293860A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the required time in manufacturing processes while improving the density of interconnection layers, by providing linear lower interconnection layers so as to have margins on the opposite sides of a contact hole without being widened in any part thereof. CONSTITUTION:Each of lower interconnection layers 1 is formed linearly so as to have margins on the opposite sides of a contact hole 3, and it is not widened in any part thereof. Each of upper interconnection layers 2 is formed so as to intersect the lower interconnection layers 1 and it is widened around the contact hole 3 formed at a predetermined intersection. Accordingly, there is no need of bending the interconnection layers 1 even near the contact holes 3. Thereby, not only the required time in the manufacturing processes can be shortened but also the density of interconnection layers can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having two types of intersecting wiring layers in a wiring portion on a chip.

[Conventional technology]

In such conventional semiconductor integrated circuit devices, it is conceivable that coordinate deviations of contact holes and the like occur between manufacturing steps. As a countermeasure to this problem, each of the two types of wiring layers that intersect with each other is given a bulge that can sufficiently contain the contact hole. That is, it is necessary to widen the distance between the two types of wiring layers and other wiring layers in the same layer in the vicinity of the contact hole. Therefore, the wiring density is generally low near the contact hole.

FIG. 2 is a top view of a semiconductor integrated circuit device for explaining a conventional example.

As shown in FIG. 2, such a semiconductor integrated circuit device includes lower wiring layers 1, 7, . . . formed on a semiconductor element (not shown).
8 and lower wiring layer 1, upper wiring layer 2 formed on 7.8
A contact hole 3 is formed at a position where the two intersect and the upper and lower layers are to be connected. Especially contact hole 3
In the vicinity of the lower wiring layer M7, the wiring density is increased by bending the wiring one after another in a step-like manner over a long period of time or in multiple steps, or by increasing the wiring density by creating a space with sufficient margin as in the lower wiring layer 8. Although wiring can be formed in a short time even with a lower value, either method is adopted.

[Problem that the invention seeks to solve]

The above-described conventional semiconductor integrated circuit device has a drawback in that the wiring density in the wiring layer, especially the lower wiring layer, is low in the vicinity of the contact hole for connecting intersecting wiring layers. On the other hand, when bending the wiring layer in a step-like manner to improve the wiring density near the contact hole,
There is a drawback that a large amount of time is required in the manufacturing process.

An object of the present invention is to provide a semiconductor integrated circuit device that can improve the conventional wiring density, reduce the time required in the manufacturing process, and reduce manufacturing costs.

[Means for solving problems]

A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device in which two types of wiring layers are electrically connected via a contact hole formed at a predetermined location where the wiring layers intersect. The lower wiring layer is formed into a straight line so as to leave a margin and eliminate any part thicker than the wiring width, and only the periphery of the contact hole that intersects the lower wiring layer and is formed at the predetermined intersection point is formed wide. and an upper wiring layer formed by:

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a top view of a wiring layer of a semiconductor integrated circuit device for explaining one embodiment of the present invention.

As shown in FIG. 1, this semiconductor integrated circuit device includes a lower wiring layer 1 and an upper wiring layer 2 formed on a semiconductor element (not shown), and a contact hole 3 formed at a predetermined position where these intersect. However, in order to guarantee the coordinate shift, the lower wiring layer 1 is formed to avoid the vicinity of the contact hole 3 in a part wider than the wiring width or in a step-like manner. In addition, the margin of the lower wiring layer 1 for the contact holes 3, that is, the lower layer contact hole interval 4, is the margin for the contact holes 3 of the upper wiring layer 2, that is, the upper layer contact hole interval. The difference is that it is smaller than 5.

By providing a semiconductor integrated circuit device having the above-described structure,
The lower layer wiring 6 does not require bending even in the vicinity of the contact hole 3, improving wiring density and eliminating the need for man-hours required for bending.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit device of the present invention has a lower wiring layer formed in a straight line so as to leave sufficient space for contact holes and eliminate thickening of the wiring width. This has the effect of reducing time and increasing wiring layer density at the same time. Also, if wiring layer density can be improved, the size of the chip can be reduced, thereby reducing manufacturing costs. It has a suppressing effect.

[Brief explanation of drawings]

FIG. 1 is a top view of a wiring layer in a semiconductor integrated circuit device for explaining an embodiment of the present invention, and FIG. 2 is a top view of a wiring layer in a semiconductor integrated circuit device for explaining a conventional example. . DESCRIPTION OF SYMBOLS 1... Lower wiring layer, 2... Upper wiring layer, 3... Contact hole, 4... Lower layer contact hole interval,
5... Upper layer contact hole spacing.

Claims (1)

[Claims] In a semiconductor integrated circuit device in which two types of wiring layers are electrically connected via a contact hole formed at a predetermined location where the wiring layers intersect, a sufficient distance is left for the contact hole and the width of the wiring is The lower wiring layer has a straight line shape so as to eliminate thick portions, and an upper wiring layer that intersects the lower wiring layer and is formed wide only around the contact hole formed at the predetermined intersection point. A semiconductor integrated circuit device characterized by: